diff -up chromium-98.0.4758.102/third_party/swiftshader/third_party/subzero/src/IceInstX8664.cpp.gcc12fix chromium-98.0.4758.102/third_party/swiftshader/third_party/subzero/src/IceInstX8664.cpp
--- chromium-98.0.4758.102/third_party/swiftshader/third_party/subzero/src/IceInstX8664.cpp.gcc12fix	2022-02-25 22:17:18.071775686 +0000
+++ chromium-98.0.4758.102/third_party/swiftshader/third_party/subzero/src/IceInstX8664.cpp	2022-02-25 22:17:40.964996468 +0000
@@ -659,6 +659,7 @@ void emitIASOpTyGPR(const Cfg *Func, Typ
   }
 }
 
+#if 0
 template <bool VarCanBeByte, bool SrcCanBeByte>
 void emitIASRegOpTyGPR(const Cfg *Func, Type Ty, const Variable *Var,
                        const Operand *Src, const GPREmitterRegOp &Emitter) {
@@ -697,6 +698,7 @@ void emitIASRegOpTyGPR(const Cfg *Func,
     llvm_unreachable("Unexpected operand type");
   }
 }
+#endif
 
 void emitIASAddrOpTyGPR(const Cfg *Func, Type Ty, const AsmAddress &Addr,
                         const Operand *Src, const GPREmitterAddrOp &Emitter) {
diff -up chromium-98.0.4758.102/third_party/swiftshader/third_party/subzero/src/IceInstX8664.h.gcc12fix chromium-98.0.4758.102/third_party/swiftshader/third_party/subzero/src/IceInstX8664.h
--- chromium-98.0.4758.102/third_party/swiftshader/third_party/subzero/src/IceInstX8664.h.gcc12fix	2022-02-25 22:17:51.409640955 +0000
+++ chromium-98.0.4758.102/third_party/swiftshader/third_party/subzero/src/IceInstX8664.h	2022-02-25 22:19:13.478847553 +0000
@@ -576,8 +576,44 @@ void emitIASXmmShift(const Cfg *Func, Ty
 /// Emit a two-operand (GPR) instruction, where the dest operand is a Variable
 /// that's guaranteed to be a register.
 template <bool VarCanBeByte = true, bool SrcCanBeByte = true>
-void emitIASRegOpTyGPR(const Cfg *Func, Type Ty, const Variable *Dst,
-                       const Operand *Src, const GPREmitterRegOp &Emitter);
+
+void emitIASRegOpTyGPR(const Cfg *Func, Type Ty, const Variable *Var,
+                       const Operand *Src, const GPREmitterRegOp &Emitter) {
+  auto *Target = InstX86Base::getTarget(Func);
+  Assembler *Asm = Func->getAssembler<Assembler>();
+  assert(Var->hasReg());
+  // We cheat a little and use GPRRegister even for byte operations.
+  GPRRegister VarReg = VarCanBeByte ? RegX8664::getEncodedGPR(Var->getRegNum())
+                                    : RegX8664::getEncodedGPR(Var->getRegNum());
+ if (const auto *SrcVar = llvm::dyn_cast<Variable>(Src)) {
+   if (SrcVar->hasReg()) {
+     GPRRegister SrcReg = SrcCanBeByte
+                              ? RegX8664::getEncodedGPR(SrcVar->getRegNum())
+                              : RegX8664::getEncodedGPR(SrcVar->getRegNum());
+     (Asm->*(Emitter.GPRGPR))(Ty, VarReg, SrcReg);
+   } else {
+     AsmAddress SrcStackAddr = AsmAddress(SrcVar, Target);
+     (Asm->*(Emitter.GPRAddr))(Ty, VarReg, SrcStackAddr);
+   }
+ } else if (const auto *Mem = llvm::dyn_cast<X86OperandMem>(Src)) {
+   Mem->emitSegmentOverride(Asm);
+   (Asm->*(Emitter.GPRAddr))(Ty, VarReg, AsmAddress(Mem, Asm, Target));
+ } else if (const auto *Imm = llvm::dyn_cast<ConstantInteger32>(Src)) {
+   (Asm->*(Emitter.GPRImm))(Ty, VarReg, AssemblerImmediate(Imm->getValue()));
+ } else if (const auto *Imm = llvm::dyn_cast<ConstantInteger64>(Src)) {
+   assert(Utils::IsInt(32, Imm->getValue()));
+   (Asm->*(Emitter.GPRImm))(Ty, VarReg, AssemblerImmediate(Imm->getValue()));
+ } else if (const auto *Reloc = llvm::dyn_cast<ConstantRelocatable>(Src)) {
+   const auto FixupKind = (Reloc->getName().hasStdString() &&
+                           Reloc->getName().toString() == GlobalOffsetTable)
+                              ? FK_GotPC
+                              : FK_Abs;
+   AssemblerFixup *Fixup = Asm->createFixup(FixupKind, Reloc);
+   (Asm->*(Emitter.GPRImm))(Ty, VarReg, AssemblerImmediate(Fixup));
+ } else {
+   llvm_unreachable("Unexpected operand type");
+ }
+}
 
 /// Instructions of the form x := op(x).
 template <typename InstX86Base::InstKindX86 K>