ceph 15.2.15 GA

Signed-off-by: Kaleb S. KEITHLEY <kkeithle@redhat.com>

0001-s390x-A-compile-hack.patch

@@ -1,65 +0,0 @@
-From a45270a441d483ce57db48cda699a0d2d9c01f18 Mon Sep 17 00:00:00 2001
-From: Boris Ranto <branto@redhat.com>
-Date: Thu, 28 Feb 2019 00:58:12 +0100
-Subject: [PATCH] s390x: A compile hack
-
-Signed-off-by: Boris Ranto <branto@redhat.com>
----
- src/rgw/rgw_dmclock_async_scheduler.cc     | 2 ++
- src/test/rgw/test_rgw_dmclock_scheduler.cc | 8 ++++----
- 2 files changed, 6 insertions(+), 4 deletions(-)
-
-diff --git a/src/rgw/rgw_dmclock_async_scheduler.cc b/src/rgw/rgw_dmclock_async_scheduler.cc
-index 18ba5a5e32..08657cf2b5 100644
---- a/src/rgw/rgw_dmclock_async_scheduler.cc
-+++ b/src/rgw/rgw_dmclock_async_scheduler.cc
-@@ -41,6 +41,7 @@ int AsyncScheduler::schedule_request_impl(const client_id& client,
-                                           const Time& time, const Cost& cost,
-                                           optional_yield yield_ctx)
- {
-+#ifdef HAVE_BOOST_CONTEXT
-     ceph_assert(yield_ctx);
- 
-     auto &yield = yield_ctx.get_yield_context();
-@@ -53,6 +54,7 @@ int AsyncScheduler::schedule_request_impl(const client_id& client,
-       else
-         return -ec.value();
-     }
-+#endif
- 
-     return 0;
- }
-diff --git a/src/test/rgw/test_rgw_dmclock_scheduler.cc b/src/test/rgw/test_rgw_dmclock_scheduler.cc
-index 4e4177cb0b..ddbfd12217 100644
---- a/src/test/rgw/test_rgw_dmclock_scheduler.cc
-+++ b/src/test/rgw/test_rgw_dmclock_scheduler.cc
-@@ -14,6 +14,8 @@
- 
- //#define BOOST_ASIO_ENABLE_HANDLER_TRACKING
- 
-+#ifdef HAVE_BOOST_CONTEXT
-+
- #include "rgw/rgw_dmclock_sync_scheduler.h"
- #include "rgw/rgw_dmclock_async_scheduler.h"
- 
-@@ -395,8 +397,6 @@ TEST(Queue, CrossExecutorRequest)
-   EXPECT_EQ(PhaseType::priority, *p2);
- }
- 
--#ifdef HAVE_BOOST_CONTEXT
--
- TEST(Queue, SpawnAsyncRequest)
- {
-   boost::asio::io_context context;
-@@ -426,6 +426,6 @@ TEST(Queue, SpawnAsyncRequest)
-   EXPECT_TRUE(context.stopped());
- }
- 
--#endif
--
- } // namespace rgw::dmclock
-+
-+#endif
--- 
-2.20.1
-

0001-src-common-crc32c_intel_fast.patch

@@ -0,0 +1,228 @@
+--- ceph-15.2.4/src/yasm-wrapper.orig	2020-06-30 11:40:51.000000000 -0400
++++ ceph-15.2.4/src/yasm-wrapper	2020-07-20 12:21:34.574980869 -0400
+@@ -1,10 +1,11 @@
+-#!/bin/sh -e
++#!/bin/sh
+ 
+ # libtool and yasm do not get along.
+ # filter out any crap that libtool feeds us that yasm does not understand.
+ #echo $0: got $*
+ new=""
+ touch=""
++object=""
+ while [ -n "$*" ]; do
+     case "$1" in
+ 	-f )
+@@ -29,6 +30,12 @@
+ 	    touch="$1"
+ 	    shift
+ 	    ;;
++	-o )
++	    shift
++	    object="$1"
++	    new="$new -o $1"
++	    shift
++	    ;;
+ 	* )
+ 	    new="$new $1"
+ 	    shift
+@@ -36,8 +43,15 @@
+     esac
+ done
+ 
+-#echo $0: yasm $new
+-yasm $new
++#echo ${0}: yasm ${new}
++yasm ${new}
++
++echo ${new} | grep -- "crc32c_intel_fast*asm\.s"
++if [ $? -ne 0 ]; then
++    touch /tmp/${object}
++    ld -r -z ibt -z shstk -z noexecstack -o ${object}.tmp ${object}
++    mv ${object}.tmp ${object}
++fi
+ 
+ [ -n "$touch" ] && touch $touch
+ 
+--- ceph-15.2.2/src/common/crc32c_intel_fast_asm.s.orig	2020-05-26 08:34:32.226201974 -0400
++++ ceph-15.2.2/src/common/crc32c_intel_fast_asm.s	2020-05-26 17:19:20.327201974 -0400
+@@ -1,5 +1,5 @@
+ ;
+-; Copyright 2012-2013 Intel Corporation All Rights Reserved.
++; Copyright 2012-2015 Intel Corporation All Rights Reserved.
+ ; All rights reserved.
+ ;
+ ; http://opensource.org/licenses/BSD-3-Clause
+@@ -59,16 +59,34 @@
+ 	xor     rbx, rbx                ;; rbx = crc1 = 0;
+ 	xor     r10, r10                ;; r10 = crc2 = 0;
+ 
++	cmp	len, %%bSize*3*2
++	jbe	%%non_prefetch
++
+  %assign i 0
+  %rep %%bSize/8 - 1
+-	crc32   rax, [bufptmp+i + 0*%%bSize]  ;; update crc0
+-	crc32   rbx, [bufptmp+i + 1*%%bSize]  ;; update crc1
+-	crc32   r10, [bufptmp+i + 2*%%bSize]  ;; update crc2
++ %if i < %%bSize*3/4
++	prefetchnta	[bufptmp+ %%bSize*3 + i*4]
++ %endif
++	crc32   rax, qword [bufptmp+i + 0*%%bSize]  ;; update crc0
++	crc32   rbx, qword [bufptmp+i + 1*%%bSize]  ;; update crc1
++	crc32   r10, qword [bufptmp+i + 2*%%bSize]  ;; update crc2
+ 	%assign i (i+8)
+  %endrep
+-	crc32   rax, [bufptmp+i + 0*%%bSize]  ;; update crc0
+-	crc32   rbx, [bufptmp+i + 1*%%bSize]  ;; update crc1
+-; SKIP  ;crc32  r10, [bufptmp+i + 2*%%bSize]  ;; update crc2
++	jmp %%next %+ %1
++
++%%non_prefetch:
++ %assign i 0
++ %rep %%bSize/8 - 1
++	crc32   rax, qword [bufptmp+i + 0*%%bSize]  ;; update crc0
++	crc32   rbx, qword [bufptmp+i + 1*%%bSize]  ;; update crc1
++	crc32  r10, qword [bufptmp+i + 2*%%bSize]  ;; update crc2
++	%assign i (i+8)
++ %endrep
++
++%%next %+ %1:
++	crc32   rax, qword [bufptmp+i + 0*%%bSize]  ;; update crc0
++	crc32   rbx, qword [bufptmp+i + 1*%%bSize]  ;; update crc1
++; SKIP	;crc32  r10, qword [bufptmp+i + 2*%%bSize]  ;; update crc2
+ 
+ 	; merge in crc0
+ 	movzx   bufp_dw, al
+@@ -180,12 +198,15 @@
+ %define crc_init_dw     r8d 
+ %endif
+ 
+-
++	endbranch
+ 	push    rdi
+ 	push    rbx
+ 
+ 	mov     rax, crc_init           ;; rax = crc_init;
+ 
++	cmp	len, 8
++	jb	less_than_8
++
+ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+ ;; 1) ALIGN: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+ 
+@@ -195,9 +216,6 @@
+ 					;; amount of the address
+ 	je      proc_block              ;; Skip if aligned
+ 
+-	cmp     len, 8
+-	jb      less_than_8
+-
+ 	;;;; Calculate CRC of unaligned bytes of the buffer (if any) ;;;;
+ 	mov     rbx, [bufptmp]          ;; load a quadword from the buffer
+ 	add     bufptmp, bufp           ;; align buffer pointer for
+@@ -233,7 +251,7 @@
+ 	jnc     bit7                    ;; jump to bit-6 if bit-7 == 0
+  %assign i 0
+  %rep 16
+-	crc32   rax, [bufptmp+i]        ;; compute crc32 of 8-byte data
++	crc32   rax, qword [bufptmp+i]  ;; compute crc32 of 8-byte data
+ 	%assign i (i+8)
+  %endrep
+ 	je      do_return               ;; return if remaining data is zero
+@@ -244,7 +262,7 @@
+ 	jnc     bit6                    ;; jump to bit-6 if bit-7 == 0
+  %assign i 0
+  %rep 8
+-	crc32   rax, [bufptmp+i]        ;; compute crc32 of 8-byte data
++	crc32   rax, qword [bufptmp+i]  ;; compute crc32 of 8-byte data
+ 	%assign i (i+8)
+  %endrep
+ 	je      do_return               ;; return if remaining data is zero
+@@ -254,7 +272,7 @@
+ 	jnc     bit5                    ;; jump to bit-5 if bit-6 == 0
+  %assign i 0
+  %rep 4
+-	crc32   rax, [bufptmp+i]        ;;    compute crc32 of 8-byte data
++	crc32   rax, qword [bufptmp+i]  ;;    compute crc32 of 8-byte data
+ 	%assign i (i+8)
+  %endrep
+ 	je      do_return               ;; return if remaining data is zero
+@@ -264,7 +282,7 @@
+ 	jnc     bit4                    ;; jump to bit-4 if bit-5 == 0
+  %assign i 0
+  %rep 2
+-	crc32   rax, [bufptmp+i]        ;;    compute crc32 of 8-byte data
++	crc32   rax, qword [bufptmp+i]  ;;    compute crc32 of 8-byte data
+ 	%assign i (i+8)
+  %endrep
+ 	je      do_return               ;; return if remaining data is zero
+@@ -272,11 +290,11 @@
+ bit4:
+ 	shl     len_b, 1                ;; shift-out MSB (bit-4)
+ 	jnc     bit3                    ;; jump to bit-3 if bit-4 == 0
+-	crc32   rax, [bufptmp]          ;; compute crc32 of 8-byte data
++	crc32   rax, qword [bufptmp]    ;; compute crc32 of 8-byte data
+ 	je      do_return               ;; return if remaining data is zero
+ 	add     bufptmp, 8              ;; buf +=8; (next 8 bytes)
+ bit3:
+-	mov     rbx, [bufptmp]          ;; load a 8-bytes from the buffer:
++	mov     rbx, qword [bufptmp]    ;; load a 8-bytes from the buffer:
+ 	shl     len_b, 1                ;; shift-out MSB (bit-3)
+ 	jnc     bit2                    ;; jump to bit-2 if bit-3 == 0
+ 	crc32   eax, ebx                ;; compute crc32 of 4-byte data
+--- ceph-15.2.2/src/common/crc32c_intel_fast_zero_asm.s.orig	2020-05-26 08:34:32.226201974 -0400
++++ ceph-15.2.2/src/common/crc32c_intel_fast_zero_asm.s	2020-05-26 17:19:32.497201974 -0400
+@@ -1,5 +1,5 @@
+ ;
+-; Copyright 2012-2013 Intel Corporation All Rights Reserved.
++; Copyright 2012-2015 Intel Corporation All Rights Reserved.
+ ; All rights reserved.
+ ;
+ ; http://opensource.org/licenses/BSD-3-Clause
+@@ -59,6 +59,19 @@
+ 	xor     rbx, rbx                ;; rbx = crc1 = 0;
+ 	xor     r10, r10                ;; r10 = crc2 = 0;
+ 
++	cmp	len, %%bSize*3*2
++	jbe	%%non_prefetch
++
++ %assign i 0
++ %rep %%bSize/8 - 1
++	crc32   rax, bufptmp  ;; update crc0
++	crc32   rbx, bufptmp  ;; update crc1
++	crc32   r10, bufptmp  ;; update crc2
++	%assign i (i+8)
++ %endrep
++	jmp %%next %+ %1
++
++%%non_prefetch:
+  %assign i 0
+  %rep %%bSize/8 - 1
+ 	crc32   rax, bufptmp  ;; update crc0
+@@ -66,6 +79,8 @@
+ 	crc32   r10, bufptmp  ;; update crc2
+ 	%assign i (i+8)
+  %endrep
++
++%%next %+ %1:
+ 	crc32   rax, bufptmp  ;; update crc0
+ 	crc32   rbx, bufptmp  ;; update crc1
+ ; SKIP  ;crc32  r10, bufptmp  ;; update crc2
+@@ -180,12 +195,15 @@
+ %define crc_init_dw     r8d
+ %endif
+ 
+-
++	endbranch
+ 	push    rdi
+ 	push    rbx
+ 
+ 	mov     rax, crc_init           ;; rax = crc_init;
+ 
++	cmp	len, 8
++	jb	less_than_8
++
+ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+ ;; 1) ALIGN: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+ 

0003-src-common-bitstr.h.patch

@@ -0,0 +1,21 @@
+--- ceph-15.1.0/src/common/bit_str.h.orig	2020-02-03 09:47:20.047149798 -0500
++++ ceph-15.1.0/src/common/bit_str.h	2020-02-03 09:47:50.213149798 -0500
+@@ -17,6 +17,7 @@
+ #include <cstdint>
+ #include <iosfwd>
+ #include <functional>
++#include <ostream>
+ 
+ namespace ceph {
+   class Formatter;
+--- ceph-15.2.4/src/global/signal_handler.h.orig        2020-07-17 12:57:54.763628429 -0400
++++ ceph-15.2.4/src/global/signal_handler.h     2020-07-17 12:58:10.610628429 -0400
+@@ -16,6 +16,8 @@
+ #define CEPH_GLOBAL_SIGNAL_HANDLER_H
+
+ #include <signal.h>
++#include <string>
++
+ #include "acconfig.h"
+
+ typedef void (*signal_handler_t)(int);

cmake-modules-BuildBoost.cmake.noautopatch

@@ -0,0 +1,13 @@
+diff --git a/cmake/modules/BuildBoost.cmake b/cmake/modules/BuildBoost.cmake
+index 2e92132366..3cb1e3d958 100644
+--- a/cmake/modules/BuildBoost.cmake
++++ b/cmake/modules/BuildBoost.cmake
+@@ -62,7 +62,7 @@ function(do_build_boost version)
+   else()
+     list(APPEND boost_features "address-model=32")
+   endif()
+-  set(BOOST_CXXFLAGS "-fPIC -w") # check on arm, etc <---XXX
++  set(BOOST_CXXFLAGS "-fPIC -w -fexceptions -fstack-protector-strong -grecord-gcc-switches -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -ftemplate-depth-1024 -fno-new-ttp-matching -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free") # check on arm, etc <---XXX
+   list(APPEND boost_features "cxxflags=${BOOST_CXXFLAGS}")
+ 
+   set(boost_with_libs)

sources

@@ -1 +1 @@
-SHA512 (ceph-14.2.0.tar.gz) = c86a335714fd5678988133ec0e60cb10cd948250a133c073d1ed055c5bba232fa6f1e102dd7fcb0c70b37a07c9c2d1220d4a1713720e4dcab9659152ee577480
+SHA512 (ceph-15.2.15.tar.gz) = e4d929ffda5c3e31767d93340fb97b5d49ca1d5641f6c30134ce5542486fc4f72684aef2ef47cb940a332e8b9144d8cec63ce8a9f86c773dbc0ccebdd8e7fb19