2020-05-26 15:15:55 +00:00
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--- ceph-15.2.2/src/common/crc32c_intel_fast_zero_asm.s.orig 2020-05-26 08:34:32.226201974 -0400
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2020-05-26 21:23:55 +00:00
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+++ ceph-15.2.2/src/common/crc32c_intel_fast_zero_asm.s 2020-05-26 17:19:32.497201974 -0400
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2020-05-26 15:15:55 +00:00
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@@ -1,5 +1,5 @@
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;
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-; Copyright 2012-2013 Intel Corporation All Rights Reserved.
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+; Copyright 2012-2015 Intel Corporation All Rights Reserved.
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; All rights reserved.
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;
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; http://opensource.org/licenses/BSD-3-Clause
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@@ -59,6 +59,19 @@
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xor rbx, rbx ;; rbx = crc1 = 0;
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xor r10, r10 ;; r10 = crc2 = 0;
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+ cmp len, %%bSize*3*2
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+ jbe %%non_prefetch
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+
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+ %assign i 0
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+ %rep %%bSize/8 - 1
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+ crc32 rax, bufptmp ;; update crc0
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+ crc32 rbx, bufptmp ;; update crc1
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+ crc32 r10, bufptmp ;; update crc2
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+ %assign i (i+8)
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+ %endrep
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2020-05-26 23:15:25 +00:00
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+ jmp %%next %+ %1
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2020-05-26 15:15:55 +00:00
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+
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+%%non_prefetch:
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%assign i 0
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%rep %%bSize/8 - 1
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crc32 rax, bufptmp ;; update crc0
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@@ -66,6 +79,8 @@
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crc32 r10, bufptmp ;; update crc2
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%assign i (i+8)
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%endrep
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+
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+%%next %+ %1:
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crc32 rax, bufptmp ;; update crc0
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crc32 rbx, bufptmp ;; update crc1
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; SKIP ;crc32 r10, bufptmp ;; update crc2
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@@ -180,12 +195,15 @@
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%define crc_init_dw r8d
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%endif
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-
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+ endbranch
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push rdi
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push rbx
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mov rax, crc_init ;; rax = crc_init;
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+ cmp len, 8
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+ jb less_than_8
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+
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; 1) ALIGN: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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