41 lines
1.6 KiB
Diff
41 lines
1.6 KiB
Diff
commit 44f814ce5066f10a3bed29c45d10e0d38f4fa433
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Author: Marcus Shawcroft <marcus.shawcroft@arm.com>
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Date: Tue Apr 15 17:46:07 2014 +0100
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[AArch64] Fix off by one error in instruction relaxation mask.
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The AArch64 TLSDESC to IE relaxation code uses a bit mask intended to
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ensure that destination register in a relaxed ldr instruction is
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always X0. The mask has an off by one error resulting in the most
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significant bit of the destination register being retained in the
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relaxed instruction. The issue generally appears when the compiler
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emits TLS accesses code under high register pressure resulting in a
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broken code sequence.
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diff --git a/bfd/elfnn-aarch64.c b/bfd/elfnn-aarch64.c
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index 42c83fb..8503419 100644
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--- a/bfd/elfnn-aarch64.c
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+++ b/bfd/elfnn-aarch64.c
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@@ -3957,7 +3957,7 @@ elfNN_aarch64_tls_relax (struct elf_aarch64_link_hash_table *globals,
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ldr xd, [x0, #:tlsdesc_lo12:var] => ldr x0, [x0, #:gottprel_lo12:var]
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*/
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insn = bfd_getl32 (contents + rel->r_offset);
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- insn &= 0xfffffff0;
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+ insn &= 0xffffffe0;
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bfd_putl32 (insn, contents + rel->r_offset);
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return bfd_reloc_continue;
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}
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diff --git a/ld/testsuite/ld-aarch64/tls-relax-gdesc-ie.s b/ld/testsuite/ld-aarch64/tls-relax-gdesc-ie.s
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index c20690c..38b3721 100644
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--- a/ld/testsuite/ld-aarch64/tls-relax-gdesc-ie.s
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+++ b/ld/testsuite/ld-aarch64/tls-relax-gdesc-ie.s
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@@ -4,7 +4,7 @@ var:
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.word 2
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.text
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adrp x0, :tlsdesc:var
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- ldr x1, [x0, #:tlsdesc_lo12:var]
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+ ldr x17, [x0, #:tlsdesc_lo12:var]
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add x0, x0, :tlsdesc_lo12:var
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.tlsdesccall var
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blr x1
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