310 lines
16 KiB
Diff
310 lines
16 KiB
Diff
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Index: gas/config/tc-s390.c
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===================================================================
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--- gas/config/tc-s390.c.orig
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+++ gas/config/tc-s390.c
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@@ -381,6 +381,8 @@ s390_parse_cpu (char *arg)
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return S390_OPCODE_Z10;
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else if (strcmp (arg, "z196") == 0)
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return S390_OPCODE_Z196;
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+ else if (strcmp (arg, "zEC12") == 0)
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+ return S390_OPCODE_ZEC12;
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else if (strcmp (arg, "all") == 0)
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return S390_OPCODE_MAXCPU - 1;
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else
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Index: gas/doc/as.texinfo
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===================================================================
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--- gas/doc/as.texinfo.orig
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+++ gas/doc/as.texinfo
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@@ -1411,7 +1411,8 @@ Select the architecture mode, either the
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Architecture (esa) or the z/Architecture mode (zarch).
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@item -march=@var{processor}
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Specify which s390 processor variant is the target, @samp{g6}, @samp{g6},
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-@samp{z900}, @samp{z990}, @samp{z9-109}, @samp{z9-ec}, or @samp{z10}.
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+@samp{z900}, @samp{z990}, @samp{z9-109}, @samp{z9-ec}, @samp{z10},
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+@samp{z196}, or @samp{zEC12}.
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@item -mregnames
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@itemx -mno-regnames
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Allow or disallow symbolic names for registers.
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Index: gas/doc/c-s390.texi
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===================================================================
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--- gas/doc/c-s390.texi.orig
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+++ gas/doc/c-s390.texi
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@@ -17,7 +17,7 @@
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The s390 version of @code{@value{AS}} supports two architectures modes
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and seven chip levels. The architecture modes are the Enterprise System
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Architecture (ESA) and the newer z/Architecture mode. The chip levels
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-are g5, g6, z900, z990, z9-109, z9-ec, z10 and z196.
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+are g5, g6, z900, z990, z9-109, z9-ec, z10, z196, and zEC12.
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@menu
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* s390 Options:: Command-line Options.
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Index: include/opcode/s390.h
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===================================================================
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--- include/opcode/s390.h.orig
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+++ include/opcode/s390.h
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@@ -40,6 +40,7 @@ enum s390_opcode_cpu_val
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S390_OPCODE_Z9_EC,
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S390_OPCODE_Z10,
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S390_OPCODE_Z196,
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+ S390_OPCODE_ZEC12,
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S390_OPCODE_MAXCPU
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};
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Index: opcodes/s390-mkopc.c
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===================================================================
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--- opcodes/s390-mkopc.c.orig
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+++ opcodes/s390-mkopc.c
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@@ -39,7 +39,8 @@ enum s390_opcode_cpu_val
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S390_OPCODE_Z9_109,
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S390_OPCODE_Z9_EC,
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S390_OPCODE_Z10,
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- S390_OPCODE_Z196
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+ S390_OPCODE_Z196,
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+ S390_OPCODE_ZEC12
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};
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struct op_struct
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@@ -365,6 +366,8 @@ main (void)
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min_cpu = S390_OPCODE_Z10;
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else if (strcmp (cpu_string, "z196") == 0)
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min_cpu = S390_OPCODE_Z196;
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+ else if (strcmp (cpu_string, "zEC12") == 0)
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+ min_cpu = S390_OPCODE_ZEC12;
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else {
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fprintf (stderr, "Couldn't parse cpu string %s\n", cpu_string);
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exit (1);
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Index: opcodes/s390-opc.c
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===================================================================
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--- opcodes/s390-opc.c.orig
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+++ opcodes/s390-opc.c
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@@ -171,50 +171,64 @@ const struct s390_operand s390_operands[
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{ 8, 8, S390_OPERAND_SIGNED },
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#define I8_32 48 /* 8 bit signed value starting at 32 */
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{ 8, 32, S390_OPERAND_SIGNED },
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-#define I16_16 49 /* 16 bit signed value starting at 16 */
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+#define I12_12 49 /* 12 bit signed value starting at 12 */
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+ { 12, 12, S390_OPERAND_SIGNED },
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+#define I16_16 50 /* 16 bit signed value starting at 16 */
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{ 16, 16, S390_OPERAND_SIGNED },
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-#define I16_32 50 /* 16 bit signed value starting at 32 */
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+#define I16_32 51 /* 16 bit signed value starting at 32 */
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{ 16, 32, S390_OPERAND_SIGNED },
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-#define I32_16 51 /* 32 bit signed value starting at 16 */
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+#define I24_24 52 /* 24 bit signed value starting at 24 */
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+ { 24, 24, S390_OPERAND_SIGNED },
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+#define I32_16 53 /* 32 bit signed value starting at 16 */
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{ 32, 16, S390_OPERAND_SIGNED },
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/* Unsigned immediate operands. */
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-#define U4_8 52 /* 4 bit unsigned value starting at 8 */
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+#define U4_8 54 /* 4 bit unsigned value starting at 8 */
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{ 4, 8, 0 },
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-#define U4_12 53 /* 4 bit unsigned value starting at 12 */
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+#define U4_12 55 /* 4 bit unsigned value starting at 12 */
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{ 4, 12, 0 },
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-#define U4_16 54 /* 4 bit unsigned value starting at 16 */
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+#define U4_16 56 /* 4 bit unsigned value starting at 16 */
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{ 4, 16, 0 },
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-#define U4_20 55 /* 4 bit unsigned value starting at 20 */
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+#define U4_20 57 /* 4 bit unsigned value starting at 20 */
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{ 4, 20, 0 },
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-#define U4_32 56 /* 4 bit unsigned value starting at 32 */
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+#define U4_24 58 /* 4 bit unsigned value starting at 24 */
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+ { 4, 24, 0 },
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+#define U4_28 59 /* 4 bit unsigned value starting at 28 */
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+ { 4, 28, 0 },
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+#define U4_32 60 /* 4 bit unsigned value starting at 32 */
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{ 4, 32, 0 },
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-#define U8_8 57 /* 8 bit unsigned value starting at 8 */
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+#define U4_36 61 /* 4 bit unsigned value starting at 36 */
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+ { 4, 36, 0 },
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+#define U8_8 62 /* 8 bit unsigned value starting at 8 */
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{ 8, 8, 0 },
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-#define U8_16 58 /* 8 bit unsigned value starting at 16 */
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+#define U8_16 63 /* 8 bit unsigned value starting at 16 */
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{ 8, 16, 0 },
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-#define U8_24 59 /* 8 bit unsigned value starting at 24 */
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+#define U8_24 64 /* 8 bit unsigned value starting at 24 */
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{ 8, 24, 0 },
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-#define U8_32 60 /* 8 bit unsigned value starting at 32 */
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+#define U8_32 65 /* 8 bit unsigned value starting at 32 */
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{ 8, 32, 0 },
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-#define U16_16 61 /* 16 bit unsigned value starting at 16 */
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+#define U16_16 66 /* 16 bit unsigned value starting at 16 */
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{ 16, 16, 0 },
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-#define U16_32 62 /* 16 bit unsigned value starting at 32 */
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+#define U16_32 67 /* 16 bit unsigned value starting at 32 */
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{ 16, 32, 0 },
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-#define U32_16 63 /* 32 bit unsigned value starting at 16 */
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+#define U32_16 68 /* 32 bit unsigned value starting at 16 */
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{ 32, 16, 0 },
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/* PC-relative address operands. */
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-#define J16_16 64 /* PC relative jump offset at 16 */
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+#define J12_12 69 /* PC relative offset at 12 */
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+ { 12, 12, S390_OPERAND_PCREL },
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+#define J16_16 70 /* PC relative offset at 16 */
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{ 16, 16, S390_OPERAND_PCREL },
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-#define J32_16 65 /* PC relative long offset at 16 */
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+#define J16_32 71 /* PC relative offset at 16 */
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+ { 16, 32, S390_OPERAND_PCREL },
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+#define J32_16 72 /* PC relative offset at 16 */
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{ 32, 16, S390_OPERAND_PCREL },
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/* Conditional mask operands. */
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-#define M_16OPT 66 /* 4 bit optional mask starting at 16 */
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+#define M_16OPT 73 /* 4 bit optional mask starting at 16 */
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{ 4, 16, S390_OPERAND_OPTIONAL },
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};
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@@ -240,13 +254,13 @@ const struct s390_operand s390_operands[
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c - control register
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d - displacement, 12 bit
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f - floating pointer register
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- fe - even numbered floating point register operand
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+ fe - fpr extended operand, a valid floating pointer register pair
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i - signed integer, 4, 8, 16 or 32 bit
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l - length, 4 or 8 bit
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p - pc relative
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r - general purpose register
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ro - optional register operand
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- re - even numbered register operand
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+ re - gpr extended operand, a valid general purpose register pair
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u - unsigned integer, 4, 8, 16 or 32 bit
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m - mode field, 4 bit
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0 - operand skipped.
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@@ -267,6 +281,8 @@ const struct s390_operand s390_operands[
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The instruction format is: INSTR_SS_LLRDRD / MASK_SS_LLRDRD. */
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#define INSTR_E 2, { 0,0,0,0,0,0 } /* e.g. pr */
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+#define INSTR_IE_UU 4, { U4_24,U4_28,0,0,0,0 } /* e.g. niai */
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+#define INSTR_MII_UPI 6, { U4_8,J12_12,I24_24 } /* e.g. bprp */
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#define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */
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#define INSTR_RIE_RRPU 6, { R_8,R_12,U4_32,J16_16,0,0 } /* e.g. crj */
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#define INSTR_RIE_RRP0 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. crjne */
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@@ -368,14 +384,16 @@ const struct s390_operand s390_operands[
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#define INSTR_RSE_CCRD 6, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lmh */
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#define INSTR_RSE_RURD 6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */
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#define INSTR_RSL_R0RD 6, { D_20,L4_8,B_16,0,0,0 } /* e.g. tp */
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+#define INSTR_RSL_LRDFU 6, { F_32,D_20,L4_8,B_16,U4_36,0 } /* e.g. cdzt */
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+#define INSTR_RSL_LRDFEU 6, { FE_32,D_20,L4_8,B_16,U4_36,0 } /* e.g. cxzt */
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#define INSTR_RSI_RRP 4, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxh */
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#define INSTR_RSY_RRRD 6, { R_8,R_12,D20_20,B_16,0,0 } /* e.g. stmy */
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#define INSTR_RSY_RERERD 6, { RE_8,RE_12,D20_20,B_16,0,0 } /* e.g. cdsy */
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#define INSTR_RSY_RURD 6, { R_8,U4_12,D20_20,B_16,0,0 } /* e.g. icmh */
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+#define INSTR_RSY_RURD2 6, { R_8,D20_20,B_16,U4_12,0,0 } /* e.g. loc */
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+#define INSTR_RSY_R0RD 6, { R_8,D20_20,B_16,0,0,0 } /* e.g. locgt */
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#define INSTR_RSY_AARD 6, { A_8,A_12,D20_20,B_16,0,0 } /* e.g. lamy */
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-#define INSTR_RSY_CCRD 6, { C_8,C_12,D20_20,B_16,0,0 } /* e.g. lamy */
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-#define INSTR_RSY_RDRM 6, { R_8,D20_20,B_16,U4_12,0,0 } /* e.g. loc */
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-#define INSTR_RSY_RDR0 6, { R_8,D20_20,B_16,0,0,0 } /* e.g. loc */
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+#define INSTR_RSY_CCRD 6, { C_8,C_12,D20_20,B_16,0,0 } /* e.g. stctg */
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#define INSTR_RS_AARD 4, { A_8,A_12,D_20,B_16,0,0 } /* e.g. lam */
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#define INSTR_RS_CCRD 4, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lctl */
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#define INSTR_RS_R0RD 4, { R_8,D_20,B_16,0,0,0 } /* e.g. sll */
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@@ -407,6 +425,7 @@ const struct s390_operand s390_operands[
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#define INSTR_SIY_IRD 6, { D20_20,B_16,I8_8,0,0,0 } /* e.g. asi */
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#define INSTR_SIL_RDI 6, { D_20,B_16,I16_32,0,0,0 } /* e.g. chhsi */
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#define INSTR_SIL_RDU 6, { D_20,B_16,U16_32,0,0,0 } /* e.g. clfhsi */
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+#define INSTR_SMI_U0RDP 6, { U4_8,J16_32,D_20,B_16,0,0 } /* e.g. bpp */
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#define INSTR_SSE_RDRD 6, { D_20,B_16,D_36,B_32,0,0 } /* e.g. mvsdk */
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#define INSTR_SS_L0RDRD 6, { D_20,L8_8,B_16,D_36,B_32,0 } /* e.g. mvc */
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#define INSTR_SS_L2RDRD 6, { D_20,B_16,D_36,L8_8,B_32,0 } /* e.g. pka */
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@@ -422,6 +441,8 @@ const struct s390_operand s390_operands[
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#define INSTR_S_RD 4, { D_20,B_16,0,0,0,0 } /* e.g. lpsw */
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#define MASK_E { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
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+#define MASK_IE_UU { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
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+#define MASK_MII_UPI { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
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#define MASK_RIE_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
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#define MASK_RIE_RRPU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
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#define MASK_RIE_RRP0 { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff }
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@@ -521,6 +542,8 @@ const struct s390_operand s390_operands[
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#define MASK_RSE_CCRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff }
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#define MASK_RSE_RURD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff }
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#define MASK_RSL_R0RD { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff }
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+#define MASK_RSL_LRDFU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
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+#define MASK_RSL_LRDFEU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
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#define MASK_RSI_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
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#define MASK_RS_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
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#define MASK_RS_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
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@@ -532,10 +555,10 @@ const struct s390_operand s390_operands[
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#define MASK_RSY_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
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#define MASK_RSY_RERERD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
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#define MASK_RSY_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
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+#define MASK_RSY_RURD2 { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
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+#define MASK_RSY_R0RD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff }
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#define MASK_RSY_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
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#define MASK_RSY_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
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-#define MASK_RSY_RDRM { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
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-#define MASK_RSY_RDR0 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff }
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#define MASK_RXE_FRRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff }
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#define MASK_RXE_FERRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff }
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#define MASK_RXE_RRRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff }
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@@ -560,6 +583,7 @@ const struct s390_operand s390_operands[
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#define MASK_SIY_IRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
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#define MASK_SIL_RDI { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
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#define MASK_SIL_RDU { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
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+#define MASK_SMI_U0RDP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
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#define MASK_SSE_RDRD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
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#define MASK_SS_L0RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
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#define MASK_SS_L2RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
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Index: opcodes/s390-opc.txt
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===================================================================
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--- opcodes/s390-opc.txt.orig
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+++ opcodes/s390-opc.txt
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@@ -1017,14 +1017,14 @@ b9f2 locr RRF_U0RR "load on condition 32
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b9f200000000 locr*16 RRF_00RR "load on condition 32 bit" z196 zarch
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b9e2 locgr RRF_U0RR "load on condition 64 bit" z196 zarch
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b9e200000000 locgr*16 RRF_00RR "load on condition 64 bit" z196 zarch
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-eb00000000f2 loc RSY_RDRM "load on condition 32 bit" z196 zarch
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-eb00000000f2 loc*12 RSY_RDR0 "load on condition 32 bit" z196 zarch
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-eb00000000e2 locg RSY_RDRM "load on condition 64 bit" z196 zarch
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-eb00000000e2 locg*12 RSY_RDR0 "load on condition 64 bit" z196 zarch
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-eb00000000f3 stoc RSY_RDRM "store on condition 32 bit" z196 zarch
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-eb00000000f3 stoc*12 RSY_RDR0 "store on condition 32 bit" z196 zarch
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-eb00000000e3 stocg RSY_RDRM "store on condition 64 bit" z196 zarch
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-eb00000000e3 stocg*12 RSY_RDR0 "store on condition 64 bit" z196 zarch
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+eb00000000f2 loc RSY_RURD2 "load on condition 32 bit" z196 zarch
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+eb00000000f2 loc*12 RSY_R0RD "load on condition 32 bit" z196 zarch
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+eb00000000e2 locg RSY_RURD2 "load on condition 64 bit" z196 zarch
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+eb00000000e2 locg*12 RSY_R0RD "load on condition 64 bit" z196 zarch
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+eb00000000f3 stoc RSY_RURD2 "store on condition 32 bit" z196 zarch
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+eb00000000f3 stoc*12 RSY_R0RD "store on condition 32 bit" z196 zarch
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+eb00000000e3 stocg RSY_RURD2 "store on condition 64 bit" z196 zarch
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+eb00000000e3 stocg*12 RSY_R0RD "store on condition 64 bit" z196 zarch
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b9f8 ark RRF_R0RR2 "add 3 operands 32 bit" z196 zarch
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b9e8 agrk RRF_R0RR2 "add 3 operands 64 bit" z196 zarch
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ec00000000d8 ahik RIE_RRI0 "add immediate 3 operands 32 bit" z196 zarch
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@@ -1104,3 +1104,26 @@ b3d8 mxtra RRF_FEUFEFE2 "multiply extend
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b3d3 sdtra RRF_FUFF2 "subtract long dfp with rounding mode" z196 zarch
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b3db sxtra RRF_FEUFEFE2 "subtract extended dfp with rounding mode" z196 zarch
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b2b8 srnmb S_RD "set 3 bit bfp rounding mode" z196 zarch
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+b2ec etnd RRE_R0 "extract transaction nesting depth" zEC12 zarch
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+e30000000025 ntstg RXY_RRRD "nontransactional store" zEC12 zarch
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+b2fc tabort S_RD "transaction abort" zEC12 zarch
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+e560 tbegin SIL_RDU "transaction begin" zEC12 zarch
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+e561 tbeginc SIL_RDU "constrained transaction begin" zEC12 zarch
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+b2f8 tend S_00 "transaction end" zEC12 zarch
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+c7 bpp SMI_U0RDP "branch prediction preload" zEC12 zarch
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+c5 bprp MII_UPI "branch prediction relative preload" zEC12 zarch
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+b2fa niai IE_UU "next instruction access intent" zEC12 zarch
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+e3000000009f lat RXY_RRRD "load and trap 32 bit" zEC12 zarch
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+e30000000085 lgat RXY_RRRD "load and trap 64 bit" zEC12 zarch
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+e300000000c8 lfhat RXY_RRRD "load high and trap" zEC12 zarch
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+e3000000009d llgfat RXY_RRRD "load logical and trap 32>64" zEC12 zarch
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+e3000000009c llgtat RXY_RRRD "load logical thirty one bits and trap 31>64" zEC12 zarch
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+eb0000000023 clt RSY_RURD "compare logical and trap 32 bit reg-mem" zEC12 zarch
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+eb0000000023 clt$12 RSY_R0RD "compare logical and trap 32 bit reg-mem" zEC12 zarch
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+eb000000002b clgt RSY_RURD "compare logical and trap 64 bit reg-mem" zEC12 zarch
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+eb000000002b clgt$12 RSY_R0RD "compare logical and trap 64 bit reg-mem" zEC12 zarch
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+ec0000000059 risbgn RIE_RRUUU "rotate then insert selected bits nocc" zEC12 zarch
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+ed00000000aa cdzt RSL_LRDFU "convert from zoned long" zEC12 zarch
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+ed00000000ab cxzt RSL_LRDFEU "convert from zoned extended" zEC12 zarch
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+ed00000000a8 czdt RSL_LRDFU "convert to zoned long" zEC12 zarch
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+ed00000000a9 czxt RSL_LRDFEU "convert to zoned extended" zEC12 zarch
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