Add support for Intel's AVX10.1 ISA.
This commit is contained in:
Nick Clifton
parent
28255cde1d
commit
e6b3d1627a
@ -2,7 +2,7 @@
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Summary: A GNU collection of binary utilities
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Name: binutils%{?_with_debug:-debug}
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Version: 2.41
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Release: 15%{?dist}
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Release: 16%{?dist}
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License: GPL-3.0-or-later AND (GPL-3.0-or-later WITH Bison-exception-2.2) AND (LGPL-2.0-or-later WITH GCC-exception-2.0) AND BSD-3-Clause AND GFDL-1.3-or-later AND GPL-2.0-or-later LGPL-2.1-or-later AND LGPL-2.0-or-later
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URL: https://sourceware.org/binutils
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@ -290,6 +290,15 @@ Patch24: binutils-aarch64-big-bti-programs.patch
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# Lifetime: Fixed in 2.42 (maybe)
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Patch25: binutils-gold-pack-relative-relocs.patch
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# Purpose: Add support for Intel's AVX10.1 architecture extension to gas.
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# Lifetime: Fixed in 2.42
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Patch26: i686-AVX10.1-part-1.patch
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Patch27: i686-AVX10.1-part-2.patch
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Patch28: i686-AVX10.1-part-3.patch
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Patch29: i686-AVX10.1-part-4.patch
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Patch30: i686-AVX10.1-part-5.patch
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Patch31: i686-AVX10.1-part-6.patch
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#----------------------------------------------------------------------------
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Provides: bundled(libiberty)
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@ -1315,6 +1324,9 @@ exit 0
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#----------------------------------------------------------------------------
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%changelog
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* Thu Dec 07 2023 Nick Clifton <nickc@redhat.com> - 2.41-16
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- Add support for Intel's AVX10.1 ISA.
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* Tue Nov 28 2023 Nick Clifton <nickc@redhat.com> - 2.41-15
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- Disable errors for executable stacks (enabled too early by previous delta).
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209
i686-AVX10.1-part-1.patch
Normal file
209
i686-AVX10.1-part-1.patch
Normal file
@ -0,0 +1,209 @@
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From e30e95759268ce5a5a1f752b3c9fa3e4a182db99 Mon Sep 17 00:00:00 2001
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From: Jan Beulich <jbeulich@suse.com>
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Date: Fri, 1 Sep 2023 12:28:57 +0200
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Subject: [PATCH] x86: correct source used for two non-AVX512 VEXWIG tests
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These shouldn't wrongly include the AVX512VL sources. Obviously the
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expectations therefore also need to change.
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---
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gas/testsuite/gas/i386/vaes-wig1.d | 118 ++++-------------------
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gas/testsuite/gas/i386/vpclmulqdq-wig1.d | 44 +++------
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2 files changed, 32 insertions(+), 130 deletions(-)
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diff --git a/gas/testsuite/gas/i386/vaes-wig1.d b/gas/testsuite/gas/i386/vaes-wig1.d
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index 8e8567e01df..9d37e52b49e 100644
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--- a/gas/testsuite/gas/i386/vaes-wig1.d
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+++ b/gas/testsuite/gas/i386/vaes-wig1.d
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@@ -1,7 +1,7 @@
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#as: -mvexwig=1
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#objdump: -dw
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#name: i386 AVX/VAES wig insns
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-#source: avx512vl_vaes.s
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+#source: vaes.s
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.*: +file format .*
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@@ -9,100 +9,24 @@
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Disassembly of section \.text:
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00000000 <_start>:
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-[ ]*[a-f0-9]+:[ ]*c4 e2 d1 de f4[ ]*vaesdec %xmm4,%xmm5,%xmm6
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-[ ]*[a-f0-9]+:[ ]*c4 e2 d1 de b4 f4 c0 1d fe ff[ ]*vaesdec -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
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-[ ]*[a-f0-9]+:[ ]*c4 e2 d1 de b2 f0 07 00 00[ ]*vaesdec 0x7f0\(%edx\),%xmm5,%xmm6
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-[ ]*[a-f0-9]+:[ ]*c4 e2 d5 de f4[ ]*vaesdec %ymm4,%ymm5,%ymm6
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-[ ]*[a-f0-9]+:[ ]*c4 e2 d5 de b4 f4 c0 1d fe ff[ ]*vaesdec -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
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-[ ]*[a-f0-9]+:[ ]*c4 e2 d5 de b2 e0 0f 00 00[ ]*vaesdec 0xfe0\(%edx\),%ymm5,%ymm6
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-[ ]*[a-f0-9]+:[ ]*c4 e2 d1 df f4[ ]*vaesdeclast %xmm4,%xmm5,%xmm6
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-[ ]*[a-f0-9]+:[ ]*c4 e2 d1 df b4 f4 c0 1d fe ff[ ]*vaesdeclast -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
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-[ ]*[a-f0-9]+:[ ]*c4 e2 d1 df b2 f0 07 00 00[ ]*vaesdeclast 0x7f0\(%edx\),%xmm5,%xmm6
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-[ ]*[a-f0-9]+:[ ]*c4 e2 d5 df f4[ ]*vaesdeclast %ymm4,%ymm5,%ymm6
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-[ ]*[a-f0-9]+:[ ]*c4 e2 d5 df b4 f4 c0 1d fe ff[ ]*vaesdeclast -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
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-[ ]*[a-f0-9]+:[ ]*c4 e2 d5 df b2 e0 0f 00 00[ ]*vaesdeclast 0xfe0\(%edx\),%ymm5,%ymm6
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-[ ]*[a-f0-9]+:[ ]*c4 e2 d1 dc f4[ ]*vaesenc %xmm4,%xmm5,%xmm6
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-[ ]*[a-f0-9]+:[ ]*c4 e2 d1 dc b4 f4 c0 1d fe ff[ ]*vaesenc -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
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-[ ]*[a-f0-9]+:[ ]*c4 e2 d1 dc b2 f0 07 00 00[ ]*vaesenc 0x7f0\(%edx\),%xmm5,%xmm6
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-[ ]*[a-f0-9]+:[ ]*c4 e2 d5 dc f4[ ]*vaesenc %ymm4,%ymm5,%ymm6
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-[ ]*[a-f0-9]+:[ ]*c4 e2 d5 dc b4 f4 c0 1d fe ff[ ]*vaesenc -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
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-[ ]*[a-f0-9]+:[ ]*c4 e2 d5 dc b2 e0 0f 00 00[ ]*vaesenc 0xfe0\(%edx\),%ymm5,%ymm6
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-[ ]*[a-f0-9]+:[ ]*c4 e2 d1 dd f4[ ]*vaesenclast %xmm4,%xmm5,%xmm6
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-[ ]*[a-f0-9]+:[ ]*c4 e2 d1 dd b4 f4 c0 1d fe ff[ ]*vaesenclast -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
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-[ ]*[a-f0-9]+:[ ]*c4 e2 d1 dd b2 f0 07 00 00[ ]*vaesenclast 0x7f0\(%edx\),%xmm5,%xmm6
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-[ ]*[a-f0-9]+:[ ]*c4 e2 d5 dd f4[ ]*vaesenclast %ymm4,%ymm5,%ymm6
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-[ ]*[a-f0-9]+:[ ]*c4 e2 d5 dd b4 f4 c0 1d fe ff[ ]*vaesenclast -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
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-[ ]*[a-f0-9]+:[ ]*c4 e2 d5 dd b2 e0 0f 00 00[ ]*vaesenclast 0xfe0\(%edx\),%ymm5,%ymm6
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-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 de f4[ ]*\{evex\} vaesdec %xmm4,%xmm5,%xmm6
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-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 de b4 f4 c0 1d fe ff[ ]*\{evex\} vaesdec -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
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-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 de 72 7f[ ]*\{evex\} vaesdec 0x7f0\(%edx\),%xmm5,%xmm6
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-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 de f4[ ]*\{evex\} vaesdec %ymm4,%ymm5,%ymm6
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-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 de b4 f4 c0 1d fe ff[ ]*\{evex\} vaesdec -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
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-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 de 72 7f[ ]*\{evex\} vaesdec 0xfe0\(%edx\),%ymm5,%ymm6
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-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 df f4[ ]*\{evex\} vaesdeclast %xmm4,%xmm5,%xmm6
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-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 df b4 f4 c0 1d fe ff[ ]*\{evex\} vaesdeclast -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
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-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 df 72 7f[ ]*\{evex\} vaesdeclast 0x7f0\(%edx\),%xmm5,%xmm6
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-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 df f4[ ]*\{evex\} vaesdeclast %ymm4,%ymm5,%ymm6
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-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 df b4 f4 c0 1d fe ff[ ]*\{evex\} vaesdeclast -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
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-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 df 72 7f[ ]*\{evex\} vaesdeclast 0xfe0\(%edx\),%ymm5,%ymm6
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-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dc f4[ ]*\{evex\} vaesenc %xmm4,%xmm5,%xmm6
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-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dc b4 f4 c0 1d fe ff[ ]*\{evex\} vaesenc -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
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-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dc 72 7f[ ]*\{evex\} vaesenc 0x7f0\(%edx\),%xmm5,%xmm6
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-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dc f4[ ]*\{evex\} vaesenc %ymm4,%ymm5,%ymm6
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-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dc b4 f4 c0 1d fe ff[ ]*\{evex\} vaesenc -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
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-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dc 72 7f[ ]*\{evex\} vaesenc 0xfe0\(%edx\),%ymm5,%ymm6
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-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dd f4[ ]*\{evex\} vaesenclast %xmm4,%xmm5,%xmm6
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-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dd b4 f4 c0 1d fe ff[ ]*\{evex\} vaesenclast -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
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-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dd 72 7f[ ]*\{evex\} vaesenclast 0x7f0\(%edx\),%xmm5,%xmm6
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-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dd f4[ ]*\{evex\} vaesenclast %ymm4,%ymm5,%ymm6
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-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dd b4 f4 c0 1d fe ff[ ]*\{evex\} vaesenclast -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
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-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dd 72 7f[ ]*\{evex\} vaesenclast 0xfe0\(%edx\),%ymm5,%ymm6
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-[ ]*[a-f0-9]+:[ ]*c4 e2 d1 de f4[ ]*vaesdec %xmm4,%xmm5,%xmm6
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-[ ]*[a-f0-9]+:[ ]*c4 e2 d1 de b4 f4 c0 1d fe ff[ ]*vaesdec -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
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-[ ]*[a-f0-9]+:[ ]*c4 e2 d1 de b2 f0 07 00 00[ ]*vaesdec 0x7f0\(%edx\),%xmm5,%xmm6
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-[ ]*[a-f0-9]+:[ ]*c4 e2 d5 de f4[ ]*vaesdec %ymm4,%ymm5,%ymm6
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-[ ]*[a-f0-9]+:[ ]*c4 e2 d5 de b4 f4 c0 1d fe ff[ ]*vaesdec -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
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-[ ]*[a-f0-9]+:[ ]*c4 e2 d5 de b2 e0 0f 00 00[ ]*vaesdec 0xfe0\(%edx\),%ymm5,%ymm6
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-[ ]*[a-f0-9]+:[ ]*c4 e2 d1 df f4[ ]*vaesdeclast %xmm4,%xmm5,%xmm6
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-[ ]*[a-f0-9]+:[ ]*c4 e2 d1 df b4 f4 c0 1d fe ff[ ]*vaesdeclast -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
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-[ ]*[a-f0-9]+:[ ]*c4 e2 d1 df b2 f0 07 00 00[ ]*vaesdeclast 0x7f0\(%edx\),%xmm5,%xmm6
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-[ ]*[a-f0-9]+:[ ]*c4 e2 d5 df f4[ ]*vaesdeclast %ymm4,%ymm5,%ymm6
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-[ ]*[a-f0-9]+:[ ]*c4 e2 d5 df b4 f4 c0 1d fe ff[ ]*vaesdeclast -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
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-[ ]*[a-f0-9]+:[ ]*c4 e2 d5 df b2 e0 0f 00 00[ ]*vaesdeclast 0xfe0\(%edx\),%ymm5,%ymm6
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-[ ]*[a-f0-9]+:[ ]*c4 e2 d1 dc f4[ ]*vaesenc %xmm4,%xmm5,%xmm6
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-[ ]*[a-f0-9]+:[ ]*c4 e2 d1 dc b4 f4 c0 1d fe ff[ ]*vaesenc -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
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-[ ]*[a-f0-9]+:[ ]*c4 e2 d1 dc b2 f0 07 00 00[ ]*vaesenc 0x7f0\(%edx\),%xmm5,%xmm6
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-[ ]*[a-f0-9]+:[ ]*c4 e2 d5 dc f4[ ]*vaesenc %ymm4,%ymm5,%ymm6
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-[ ]*[a-f0-9]+:[ ]*c4 e2 d5 dc b4 f4 c0 1d fe ff[ ]*vaesenc -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
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-[ ]*[a-f0-9]+:[ ]*c4 e2 d5 dc b2 e0 0f 00 00[ ]*vaesenc 0xfe0\(%edx\),%ymm5,%ymm6
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-[ ]*[a-f0-9]+:[ ]*c4 e2 d1 dd f4[ ]*vaesenclast %xmm4,%xmm5,%xmm6
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-[ ]*[a-f0-9]+:[ ]*c4 e2 d1 dd b4 f4 c0 1d fe ff[ ]*vaesenclast -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
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-[ ]*[a-f0-9]+:[ ]*c4 e2 d1 dd b2 f0 07 00 00[ ]*vaesenclast 0x7f0\(%edx\),%xmm5,%xmm6
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-[ ]*[a-f0-9]+:[ ]*c4 e2 d5 dd f4[ ]*vaesenclast %ymm4,%ymm5,%ymm6
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-[ ]*[a-f0-9]+:[ ]*c4 e2 d5 dd b4 f4 c0 1d fe ff[ ]*vaesenclast -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
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-[ ]*[a-f0-9]+:[ ]*c4 e2 d5 dd b2 e0 0f 00 00[ ]*vaesenclast 0xfe0\(%edx\),%ymm5,%ymm6
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-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 de f4[ ]*\{evex\} vaesdec %xmm4,%xmm5,%xmm6
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-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 de b4 f4 c0 1d fe ff[ ]*\{evex\} vaesdec -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
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-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 de 72 7f[ ]*\{evex\} vaesdec 0x7f0\(%edx\),%xmm5,%xmm6
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-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 de f4[ ]*\{evex\} vaesdec %ymm4,%ymm5,%ymm6
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-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 de b4 f4 c0 1d fe ff[ ]*\{evex\} vaesdec -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
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-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 de 72 7f[ ]*\{evex\} vaesdec 0xfe0\(%edx\),%ymm5,%ymm6
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-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 df f4[ ]*\{evex\} vaesdeclast %xmm4,%xmm5,%xmm6
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-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 df b4 f4 c0 1d fe ff[ ]*\{evex\} vaesdeclast -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
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-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 df 72 7f[ ]*\{evex\} vaesdeclast 0x7f0\(%edx\),%xmm5,%xmm6
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-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 df f4[ ]*\{evex\} vaesdeclast %ymm4,%ymm5,%ymm6
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-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 df b4 f4 c0 1d fe ff[ ]*\{evex\} vaesdeclast -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
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-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 df 72 7f[ ]*\{evex\} vaesdeclast 0xfe0\(%edx\),%ymm5,%ymm6
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-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dc f4[ ]*\{evex\} vaesenc %xmm4,%xmm5,%xmm6
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-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dc b4 f4 c0 1d fe ff[ ]*\{evex\} vaesenc -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
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-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dc 72 7f[ ]*\{evex\} vaesenc 0x7f0\(%edx\),%xmm5,%xmm6
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-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dc f4[ ]*\{evex\} vaesenc %ymm4,%ymm5,%ymm6
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-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dc b4 f4 c0 1d fe ff[ ]*\{evex\} vaesenc -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
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-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dc 72 7f[ ]*\{evex\} vaesenc 0xfe0\(%edx\),%ymm5,%ymm6
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-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dd f4[ ]*\{evex\} vaesenclast %xmm4,%xmm5,%xmm6
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-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dd b4 f4 c0 1d fe ff[ ]*\{evex\} vaesenclast -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
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-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dd 72 7f[ ]*\{evex\} vaesenclast 0x7f0\(%edx\),%xmm5,%xmm6
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-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dd f4[ ]*\{evex\} vaesenclast %ymm4,%ymm5,%ymm6
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-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dd b4 f4 c0 1d fe ff[ ]*\{evex\} vaesenclast -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
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-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dd 72 7f[ ]*\{evex\} vaesenclast 0xfe0\(%edx\),%ymm5,%ymm6
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+[ ]*[a-f0-9]+: c4 e2 cd dc d4 vaesenc %ymm4,%ymm6,%ymm2
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+[ ]*[a-f0-9]+: c4 e2 cd dc 39 vaesenc \(%ecx\),%ymm6,%ymm7
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+[ ]*[a-f0-9]+: c4 e2 cd dd d4 vaesenclast %ymm4,%ymm6,%ymm2
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+[ ]*[a-f0-9]+: c4 e2 cd dd 39 vaesenclast \(%ecx\),%ymm6,%ymm7
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+[ ]*[a-f0-9]+: c4 e2 cd de d4 vaesdec %ymm4,%ymm6,%ymm2
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+[ ]*[a-f0-9]+: c4 e2 cd de 39 vaesdec \(%ecx\),%ymm6,%ymm7
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+[ ]*[a-f0-9]+: c4 e2 cd df d4 vaesdeclast %ymm4,%ymm6,%ymm2
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+[ ]*[a-f0-9]+: c4 e2 cd df 39 vaesdeclast \(%ecx\),%ymm6,%ymm7
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+[ ]*[a-f0-9]+: c4 e2 cd dc d4 vaesenc %ymm4,%ymm6,%ymm2
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+[ ]*[a-f0-9]+: c4 e2 cd dc 39 vaesenc \(%ecx\),%ymm6,%ymm7
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+[ ]*[a-f0-9]+: c4 e2 cd dc 39 vaesenc \(%ecx\),%ymm6,%ymm7
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+[ ]*[a-f0-9]+: c4 e2 cd dd d4 vaesenclast %ymm4,%ymm6,%ymm2
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+[ ]*[a-f0-9]+: c4 e2 cd dd 39 vaesenclast \(%ecx\),%ymm6,%ymm7
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+[ ]*[a-f0-9]+: c4 e2 cd dd 39 vaesenclast \(%ecx\),%ymm6,%ymm7
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+[ ]*[a-f0-9]+: c4 e2 cd de d4 vaesdec %ymm4,%ymm6,%ymm2
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+[ ]*[a-f0-9]+: c4 e2 cd de 39 vaesdec \(%ecx\),%ymm6,%ymm7
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+[ ]*[a-f0-9]+: c4 e2 cd de 39 vaesdec \(%ecx\),%ymm6,%ymm7
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+[ ]*[a-f0-9]+: c4 e2 cd df d4 vaesdeclast %ymm4,%ymm6,%ymm2
|
||||
+[ ]*[a-f0-9]+: c4 e2 cd df 39 vaesdeclast \(%ecx\),%ymm6,%ymm7
|
||||
+[ ]*[a-f0-9]+: c4 e2 cd df 39 vaesdeclast \(%ecx\),%ymm6,%ymm7
|
||||
#pass
|
||||
diff --git a/gas/testsuite/gas/i386/vpclmulqdq-wig1.d b/gas/testsuite/gas/i386/vpclmulqdq-wig1.d
|
||||
index 843bf56bc21..52bb1651201 100644
|
||||
--- a/gas/testsuite/gas/i386/vpclmulqdq-wig1.d
|
||||
+++ b/gas/testsuite/gas/i386/vpclmulqdq-wig1.d
|
||||
@@ -1,7 +1,7 @@
|
||||
#as: -mvexwig=1
|
||||
#objdump: -dw
|
||||
#name: i386 AVX/VPCLMULQDQ wig insns
|
||||
-#source: avx512vl_vpclmulqdq.s
|
||||
+#source: vpclmulqdq.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
@@ -9,36 +9,14 @@
|
||||
Disassembly of section \.text:
|
||||
|
||||
00000000 <_start>:
|
||||
-[ ]*[a-f0-9]+:[ ]*c4 e3 e9 44 da ab[ ]*vpclmulqdq \$0xab,%xmm2,%xmm2,%xmm3
|
||||
-[ ]*[a-f0-9]+:[ ]*c4 e3 e9 44 9c f4 c0 1d fe ff 7b[ ]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm2,%xmm3
|
||||
-[ ]*[a-f0-9]+:[ ]*c4 e3 e9 44 9a f0 07 00 00 7b[ ]*vpclmulqdq \$0x7b,0x7f0\(%edx\),%xmm2,%xmm3
|
||||
-[ ]*[a-f0-9]+:[ ]*c4 e3 d5 44 e1 ab[ ]*vpclmulqdq \$0xab,%ymm1,%ymm5,%ymm4
|
||||
-[ ]*[a-f0-9]+:[ ]*c4 e3 d5 44 a4 f4 c0 1d fe ff 7b[ ]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm5,%ymm4
|
||||
-[ ]*[a-f0-9]+:[ ]*c4 e3 d5 44 a2 e0 0f 00 00 7b[ ]*vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm5,%ymm4
|
||||
-[ ]*[a-f0-9]+:[ ]*62 f3 6d 08 44 da ab[ ]*\{evex\} vpclmulqdq \$0xab,%xmm2,%xmm2,%xmm3
|
||||
-[ ]*[a-f0-9]+:[ ]*62 f3 6d 08 44 9c f4 c0 1d fe ff 7b[ ]*\{evex\} vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm2,%xmm3
|
||||
-[ ]*[a-f0-9]+:[ ]*62 f3 6d 08 44 5a 7f 7b[ ]*\{evex\} vpclmulqdq \$0x7b,0x7f0\(%edx\),%xmm2,%xmm3
|
||||
-[ ]*[a-f0-9]+:[ ]*62 f3 55 28 44 e1 ab[ ]*\{evex\} vpclmulqdq \$0xab,%ymm1,%ymm5,%ymm4
|
||||
-[ ]*[a-f0-9]+:[ ]*62 f3 55 28 44 a4 f4 c0 1d fe ff 7b[ ]*\{evex\} vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm5,%ymm4
|
||||
-[ ]*[a-f0-9]+:[ ]*62 f3 55 28 44 62 7f 7b[ ]*\{evex\} vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm5,%ymm4
|
||||
-[ ]*[a-f0-9]+:[ ]*62 f3 65 08 44 e2 11[ ]*\{evex\} vpclmulhqhqdq %xmm2,%xmm3,%xmm4
|
||||
-[ ]*[a-f0-9]+:[ ]*62 f3 5d 08 44 eb 01[ ]*\{evex\} vpclmulhqlqdq %xmm3,%xmm4,%xmm5
|
||||
-[ ]*[a-f0-9]+:[ ]*62 f3 55 08 44 f4 10[ ]*\{evex\} vpclmullqhqdq %xmm4,%xmm5,%xmm6
|
||||
-[ ]*[a-f0-9]+:[ ]*62 f3 4d 08 44 fd 00[ ]*\{evex\} vpclmullqlqdq %xmm5,%xmm6,%xmm7
|
||||
-[ ]*[a-f0-9]+:[ ]*62 f3 6d 28 44 d9 11[ ]*\{evex\} vpclmulhqhqdq %ymm1,%ymm2,%ymm3
|
||||
-[ ]*[a-f0-9]+:[ ]*62 f3 65 28 44 e2 01[ ]*\{evex\} vpclmulhqlqdq %ymm2,%ymm3,%ymm4
|
||||
-[ ]*[a-f0-9]+:[ ]*62 f3 5d 28 44 eb 10[ ]*\{evex\} vpclmullqhqdq %ymm3,%ymm4,%ymm5
|
||||
-[ ]*[a-f0-9]+:[ ]*62 f3 55 28 44 f4 00[ ]*\{evex\} vpclmullqlqdq %ymm4,%ymm5,%ymm6
|
||||
-[ ]*[a-f0-9]+:[ ]*c4 e3 d1 44 db ab[ ]*vpclmulqdq \$0xab,%xmm3,%xmm5,%xmm3
|
||||
-[ ]*[a-f0-9]+:[ ]*c4 e3 d1 44 9c f4 c0 1d fe ff 7b[ ]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm5,%xmm3
|
||||
-[ ]*[a-f0-9]+:[ ]*c4 e3 d1 44 9a f0 07 00 00 7b[ ]*vpclmulqdq \$0x7b,0x7f0\(%edx\),%xmm5,%xmm3
|
||||
-[ ]*[a-f0-9]+:[ ]*c4 e3 ed 44 d2 ab[ ]*vpclmulqdq \$0xab,%ymm2,%ymm2,%ymm2
|
||||
-[ ]*[a-f0-9]+:[ ]*c4 e3 ed 44 94 f4 c0 1d fe ff 7b[ ]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm2,%ymm2
|
||||
-[ ]*[a-f0-9]+:[ ]*c4 e3 ed 44 92 e0 0f 00 00 7b[ ]*vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm2,%ymm2
|
||||
-[ ]*[a-f0-9]+:[ ]*62 f3 55 08 44 db ab[ ]*\{evex\} vpclmulqdq \$0xab,%xmm3,%xmm5,%xmm3
|
||||
-[ ]*[a-f0-9]+:[ ]*62 f3 55 08 44 9c f4 c0 1d fe ff 7b[ ]*\{evex\} vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm5,%xmm3
|
||||
-[ ]*[a-f0-9]+:[ ]*62 f3 55 08 44 5a 7f 7b[ ]*\{evex\} vpclmulqdq \$0x7b,0x7f0\(%edx\),%xmm5,%xmm3
|
||||
-[ ]*[a-f0-9]+:[ ]*62 f3 6d 28 44 d2 ab[ ]*\{evex\} vpclmulqdq \$0xab,%ymm2,%ymm2,%ymm2
|
||||
-[ ]*[a-f0-9]+:[ ]*62 f3 6d 28 44 94 f4 c0 1d fe ff 7b[ ]*\{evex\} vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm2,%ymm2
|
||||
-[ ]*[a-f0-9]+:[ ]*62 f3 6d 28 44 52 7f 7b[ ]*\{evex\} vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm2,%ymm2
|
||||
+[ ]*[a-f0-9]+:[ ]*c4 e3 d5 44 f4 ab[ ]*vpclmulqdq \$0xab,%ymm4,%ymm5,%ymm6
|
||||
+[ ]*[a-f0-9]+:[ ]*c4 e3 d5 44 b4 f4 c0 1d fe ff 7b[ ]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
|
||||
+[ ]*[a-f0-9]+:[ ]*c4 e3 d5 44 b2 e0 0f 00 00 7b[ ]*vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm5,%ymm6
|
||||
+[ ]*[a-f0-9]+:[ ]*c4 e3 ed 44 d9 11[ ]*vpclmulhqhqdq %ymm1,%ymm2,%ymm3
|
||||
+[ ]*[a-f0-9]+:[ ]*c4 e3 e5 44 e2 01[ ]*vpclmulhqlqdq %ymm2,%ymm3,%ymm4
|
||||
+[ ]*[a-f0-9]+:[ ]*c4 e3 dd 44 eb 10[ ]*vpclmullqhqdq %ymm3,%ymm4,%ymm5
|
||||
+[ ]*[a-f0-9]+:[ ]*c4 e3 d5 44 f4 00[ ]*vpclmullqlqdq %ymm4,%ymm5,%ymm6
|
||||
+[ ]*[a-f0-9]+:[ ]*c4 e3 d5 44 f4 ab[ ]*vpclmulqdq \$0xab,%ymm4,%ymm5,%ymm6
|
||||
+[ ]*[a-f0-9]+:[ ]*c4 e3 d5 44 b4 f4 c0 1d fe ff 7b[ ]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
|
||||
+[ ]*[a-f0-9]+:[ ]*c4 e3 d5 44 b2 e0 0f 00 00 7b[ ]*vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm5,%ymm6
|
||||
#pass
|
||||
--
|
||||
2.43.0
|
||||
|
||||
379
i686-AVX10.1-part-2.patch
Normal file
379
i686-AVX10.1-part-2.patch
Normal file
@ -0,0 +1,379 @@
|
||||
From dfab07b9ead66f08661325c03175e1df9210ccd7 Mon Sep 17 00:00:00 2001
|
||||
From: Jan Beulich <jbeulich@suse.com>
|
||||
Date: Fri, 1 Sep 2023 12:29:44 +0200
|
||||
Subject: [PATCH] x86: unindent most of set_cpu_arch()
|
||||
|
||||
Inverting the initial if()'s condition allows to move out the bulk of
|
||||
the function by a level, improving readability at least a bit. While
|
||||
doing that also pull the push/pop handling up first, such that "else if"
|
||||
after "return" isn't needed anymore; the order in which special cases
|
||||
are checked doesn't really matter.
|
||||
---
|
||||
gas/config/tc-i386.c | 305 ++++++++++++++++++++++---------------------
|
||||
1 file changed, 154 insertions(+), 151 deletions(-)
|
||||
|
||||
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
|
||||
index 19a5f2d61e5..00abfc78264 100644
|
||||
--- a/gas/config/tc-i386.c
|
||||
+++ b/gas/config/tc-i386.c
|
||||
@@ -2793,29 +2793,134 @@ set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
|
||||
bool no_cond_jump_promotion;
|
||||
} arch_stack_entry;
|
||||
static const arch_stack_entry *arch_stack_top;
|
||||
+ char *s;
|
||||
+ int e;
|
||||
+ const char *string;
|
||||
+ unsigned int j = 0;
|
||||
+ i386_cpu_flags flags;
|
||||
|
||||
SKIP_WHITESPACE ();
|
||||
|
||||
- if (!is_end_of_line[(unsigned char) *input_line_pointer])
|
||||
+ if (is_end_of_line[(unsigned char) *input_line_pointer])
|
||||
+ {
|
||||
+ as_bad (_("missing cpu architecture"));
|
||||
+ input_line_pointer++;
|
||||
+ return;
|
||||
+ }
|
||||
+
|
||||
+ e = get_symbol_name (&s);
|
||||
+ string = s;
|
||||
+
|
||||
+ if (strcmp (string, "push") == 0)
|
||||
+ {
|
||||
+ arch_stack_entry *top = XNEW (arch_stack_entry);
|
||||
+
|
||||
+ top->name = cpu_arch_name;
|
||||
+ if (cpu_sub_arch_name)
|
||||
+ top->sub_name = xstrdup (cpu_sub_arch_name);
|
||||
+ else
|
||||
+ top->sub_name = NULL;
|
||||
+ top->flags = cpu_arch_flags;
|
||||
+ top->isa = cpu_arch_isa;
|
||||
+ top->isa_flags = cpu_arch_isa_flags;
|
||||
+ top->flag_code = flag_code;
|
||||
+ top->stackop_size = stackop_size;
|
||||
+ top->no_cond_jump_promotion = no_cond_jump_promotion;
|
||||
+
|
||||
+ top->prev = arch_stack_top;
|
||||
+ arch_stack_top = top;
|
||||
+
|
||||
+ (void) restore_line_pointer (e);
|
||||
+ demand_empty_rest_of_line ();
|
||||
+ return;
|
||||
+ }
|
||||
+
|
||||
+ if (strcmp (string, "pop") == 0)
|
||||
{
|
||||
- char *s;
|
||||
- int e = get_symbol_name (&s);
|
||||
- const char *string = s;
|
||||
- unsigned int j = 0;
|
||||
- i386_cpu_flags flags;
|
||||
+ const arch_stack_entry *top = arch_stack_top;
|
||||
|
||||
- if (strcmp (string, "default") == 0)
|
||||
+ if (!top)
|
||||
+ as_bad (_(".arch stack is empty"));
|
||||
+ else if (top->flag_code != flag_code
|
||||
+ || top->stackop_size != stackop_size)
|
||||
+ {
|
||||
+ static const unsigned int bits[] = {
|
||||
+ [CODE_16BIT] = 16,
|
||||
+ [CODE_32BIT] = 32,
|
||||
+ [CODE_64BIT] = 64,
|
||||
+ };
|
||||
+
|
||||
+ as_bad (_("this `.arch pop' requires `.code%u%s' to be in effect"),
|
||||
+ bits[top->flag_code],
|
||||
+ top->stackop_size == LONG_MNEM_SUFFIX ? "gcc" : "");
|
||||
+ }
|
||||
+ else
|
||||
+ {
|
||||
+ arch_stack_top = top->prev;
|
||||
+
|
||||
+ cpu_arch_name = top->name;
|
||||
+ free (cpu_sub_arch_name);
|
||||
+ cpu_sub_arch_name = top->sub_name;
|
||||
+ cpu_arch_flags = top->flags;
|
||||
+ cpu_arch_isa = top->isa;
|
||||
+ cpu_arch_isa_flags = top->isa_flags;
|
||||
+ no_cond_jump_promotion = top->no_cond_jump_promotion;
|
||||
+
|
||||
+ XDELETE (top);
|
||||
+ }
|
||||
+
|
||||
+ (void) restore_line_pointer (e);
|
||||
+ demand_empty_rest_of_line ();
|
||||
+ return;
|
||||
+ }
|
||||
+
|
||||
+ if (strcmp (string, "default") == 0)
|
||||
+ {
|
||||
+ if (strcmp (default_arch, "iamcu") == 0)
|
||||
+ string = default_arch;
|
||||
+ else
|
||||
{
|
||||
- if (strcmp (default_arch, "iamcu") == 0)
|
||||
- string = default_arch;
|
||||
+ static const i386_cpu_flags cpu_unknown_flags = CPU_UNKNOWN_FLAGS;
|
||||
+
|
||||
+ cpu_arch_name = NULL;
|
||||
+ free (cpu_sub_arch_name);
|
||||
+ cpu_sub_arch_name = NULL;
|
||||
+ cpu_arch_flags = cpu_unknown_flags;
|
||||
+ if (flag_code == CODE_64BIT)
|
||||
+ {
|
||||
+ cpu_arch_flags.bitfield.cpu64 = 1;
|
||||
+ cpu_arch_flags.bitfield.cpuno64 = 0;
|
||||
+ }
|
||||
else
|
||||
{
|
||||
- static const i386_cpu_flags cpu_unknown_flags = CPU_UNKNOWN_FLAGS;
|
||||
+ cpu_arch_flags.bitfield.cpu64 = 0;
|
||||
+ cpu_arch_flags.bitfield.cpuno64 = 1;
|
||||
+ }
|
||||
+ cpu_arch_isa = PROCESSOR_UNKNOWN;
|
||||
+ cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].enable;
|
||||
+ if (!cpu_arch_tune_set)
|
||||
+ {
|
||||
+ cpu_arch_tune = cpu_arch_isa;
|
||||
+ cpu_arch_tune_flags = cpu_arch_isa_flags;
|
||||
+ }
|
||||
+
|
||||
+ j = ARRAY_SIZE (cpu_arch) + 1;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ for (; j < ARRAY_SIZE (cpu_arch); j++)
|
||||
+ {
|
||||
+ if (strcmp (string + (*string == '.'), cpu_arch[j].name) == 0
|
||||
+ && (*string == '.') == (cpu_arch[j].type == PROCESSOR_NONE))
|
||||
+ {
|
||||
+ if (*string != '.')
|
||||
+ {
|
||||
+ check_cpu_arch_compatible (string, cpu_arch[j].enable);
|
||||
|
||||
- cpu_arch_name = NULL;
|
||||
+ cpu_arch_name = cpu_arch[j].name;
|
||||
free (cpu_sub_arch_name);
|
||||
cpu_sub_arch_name = NULL;
|
||||
- cpu_arch_flags = cpu_unknown_flags;
|
||||
+ cpu_arch_flags = cpu_arch[j].enable;
|
||||
if (flag_code == CODE_64BIT)
|
||||
{
|
||||
cpu_arch_flags.bitfield.cpu64 = 1;
|
||||
@@ -2826,173 +2931,71 @@ set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
|
||||
cpu_arch_flags.bitfield.cpu64 = 0;
|
||||
cpu_arch_flags.bitfield.cpuno64 = 1;
|
||||
}
|
||||
- cpu_arch_isa = PROCESSOR_UNKNOWN;
|
||||
- cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].enable;
|
||||
+ cpu_arch_isa = cpu_arch[j].type;
|
||||
+ cpu_arch_isa_flags = cpu_arch[j].enable;
|
||||
if (!cpu_arch_tune_set)
|
||||
{
|
||||
cpu_arch_tune = cpu_arch_isa;
|
||||
cpu_arch_tune_flags = cpu_arch_isa_flags;
|
||||
}
|
||||
-
|
||||
- j = ARRAY_SIZE (cpu_arch) + 1;
|
||||
+ pre_386_16bit_warned = false;
|
||||
+ break;
|
||||
}
|
||||
- }
|
||||
- else if (strcmp (string, "push") == 0)
|
||||
- {
|
||||
- arch_stack_entry *top = XNEW (arch_stack_entry);
|
||||
|
||||
- top->name = cpu_arch_name;
|
||||
- if (cpu_sub_arch_name)
|
||||
- top->sub_name = xstrdup (cpu_sub_arch_name);
|
||||
- else
|
||||
- top->sub_name = NULL;
|
||||
- top->flags = cpu_arch_flags;
|
||||
- top->isa = cpu_arch_isa;
|
||||
- top->isa_flags = cpu_arch_isa_flags;
|
||||
- top->flag_code = flag_code;
|
||||
- top->stackop_size = stackop_size;
|
||||
- top->no_cond_jump_promotion = no_cond_jump_promotion;
|
||||
+ if (cpu_flags_all_zero (&cpu_arch[j].enable))
|
||||
+ continue;
|
||||
|
||||
- top->prev = arch_stack_top;
|
||||
- arch_stack_top = top;
|
||||
+ flags = cpu_flags_or (cpu_arch_flags, cpu_arch[j].enable);
|
||||
|
||||
- (void) restore_line_pointer (e);
|
||||
- demand_empty_rest_of_line ();
|
||||
- return;
|
||||
- }
|
||||
- else if (strcmp (string, "pop") == 0)
|
||||
- {
|
||||
- const arch_stack_entry *top = arch_stack_top;
|
||||
-
|
||||
- if (!top)
|
||||
- as_bad (_(".arch stack is empty"));
|
||||
- else if (top->flag_code != flag_code
|
||||
- || top->stackop_size != stackop_size)
|
||||
+ if (!cpu_flags_equal (&flags, &cpu_arch_flags))
|
||||
{
|
||||
- static const unsigned int bits[] = {
|
||||
- [CODE_16BIT] = 16,
|
||||
- [CODE_32BIT] = 32,
|
||||
- [CODE_64BIT] = 64,
|
||||
- };
|
||||
-
|
||||
- as_bad (_("this `.arch pop' requires `.code%u%s' to be in effect"),
|
||||
- bits[top->flag_code],
|
||||
- top->stackop_size == LONG_MNEM_SUFFIX ? "gcc" : "");
|
||||
+ extend_cpu_sub_arch_name (string + 1);
|
||||
+ cpu_arch_flags = flags;
|
||||
+ cpu_arch_isa_flags = flags;
|
||||
}
|
||||
else
|
||||
- {
|
||||
- arch_stack_top = top->prev;
|
||||
-
|
||||
- cpu_arch_name = top->name;
|
||||
- free (cpu_sub_arch_name);
|
||||
- cpu_sub_arch_name = top->sub_name;
|
||||
- cpu_arch_flags = top->flags;
|
||||
- cpu_arch_isa = top->isa;
|
||||
- cpu_arch_isa_flags = top->isa_flags;
|
||||
- no_cond_jump_promotion = top->no_cond_jump_promotion;
|
||||
-
|
||||
- XDELETE (top);
|
||||
- }
|
||||
+ cpu_arch_isa_flags
|
||||
+ = cpu_flags_or (cpu_arch_isa_flags, cpu_arch[j].enable);
|
||||
|
||||
(void) restore_line_pointer (e);
|
||||
demand_empty_rest_of_line ();
|
||||
return;
|
||||
}
|
||||
+ }
|
||||
|
||||
- for (; j < ARRAY_SIZE (cpu_arch); j++)
|
||||
- {
|
||||
- if (strcmp (string + (*string == '.'), cpu_arch[j].name) == 0
|
||||
- && (*string == '.') == (cpu_arch[j].type == PROCESSOR_NONE))
|
||||
- {
|
||||
- if (*string != '.')
|
||||
- {
|
||||
- check_cpu_arch_compatible (string, cpu_arch[j].enable);
|
||||
-
|
||||
- cpu_arch_name = cpu_arch[j].name;
|
||||
- free (cpu_sub_arch_name);
|
||||
- cpu_sub_arch_name = NULL;
|
||||
- cpu_arch_flags = cpu_arch[j].enable;
|
||||
- if (flag_code == CODE_64BIT)
|
||||
- {
|
||||
- cpu_arch_flags.bitfield.cpu64 = 1;
|
||||
- cpu_arch_flags.bitfield.cpuno64 = 0;
|
||||
- }
|
||||
- else
|
||||
- {
|
||||
- cpu_arch_flags.bitfield.cpu64 = 0;
|
||||
- cpu_arch_flags.bitfield.cpuno64 = 1;
|
||||
- }
|
||||
- cpu_arch_isa = cpu_arch[j].type;
|
||||
- cpu_arch_isa_flags = cpu_arch[j].enable;
|
||||
- if (!cpu_arch_tune_set)
|
||||
- {
|
||||
- cpu_arch_tune = cpu_arch_isa;
|
||||
- cpu_arch_tune_flags = cpu_arch_isa_flags;
|
||||
- }
|
||||
- pre_386_16bit_warned = false;
|
||||
- break;
|
||||
- }
|
||||
-
|
||||
- if (cpu_flags_all_zero (&cpu_arch[j].enable))
|
||||
- continue;
|
||||
-
|
||||
- flags = cpu_flags_or (cpu_arch_flags,
|
||||
- cpu_arch[j].enable);
|
||||
-
|
||||
- if (!cpu_flags_equal (&flags, &cpu_arch_flags))
|
||||
- {
|
||||
- extend_cpu_sub_arch_name (string + 1);
|
||||
- cpu_arch_flags = flags;
|
||||
- cpu_arch_isa_flags = flags;
|
||||
- }
|
||||
- else
|
||||
- cpu_arch_isa_flags
|
||||
- = cpu_flags_or (cpu_arch_isa_flags,
|
||||
- cpu_arch[j].enable);
|
||||
- (void) restore_line_pointer (e);
|
||||
- demand_empty_rest_of_line ();
|
||||
- return;
|
||||
- }
|
||||
- }
|
||||
-
|
||||
- if (startswith (string, ".no") && j >= ARRAY_SIZE (cpu_arch))
|
||||
- {
|
||||
- /* Disable an ISA extension. */
|
||||
- for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
|
||||
- if (cpu_arch[j].type == PROCESSOR_NONE
|
||||
- && strcmp (string + 3, cpu_arch[j].name) == 0)
|
||||
+ if (startswith (string, ".no") && j >= ARRAY_SIZE (cpu_arch))
|
||||
+ {
|
||||
+ /* Disable an ISA extension. */
|
||||
+ for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
|
||||
+ if (cpu_arch[j].type == PROCESSOR_NONE
|
||||
+ && strcmp (string + 3, cpu_arch[j].name) == 0)
|
||||
+ {
|
||||
+ flags = cpu_flags_and_not (cpu_arch_flags, cpu_arch[j].disable);
|
||||
+ if (!cpu_flags_equal (&flags, &cpu_arch_flags))
|
||||
{
|
||||
- flags = cpu_flags_and_not (cpu_arch_flags,
|
||||
- cpu_arch[j].disable);
|
||||
- if (!cpu_flags_equal (&flags, &cpu_arch_flags))
|
||||
- {
|
||||
- extend_cpu_sub_arch_name (string + 1);
|
||||
- cpu_arch_flags = flags;
|
||||
- cpu_arch_isa_flags = flags;
|
||||
- }
|
||||
- (void) restore_line_pointer (e);
|
||||
- demand_empty_rest_of_line ();
|
||||
- return;
|
||||
+ extend_cpu_sub_arch_name (string + 1);
|
||||
+ cpu_arch_flags = flags;
|
||||
+ cpu_arch_isa_flags = flags;
|
||||
}
|
||||
- }
|
||||
-
|
||||
- if (j == ARRAY_SIZE (cpu_arch))
|
||||
- as_bad (_("no such architecture: `%s'"), string);
|
||||
|
||||
- *input_line_pointer = e;
|
||||
+ (void) restore_line_pointer (e);
|
||||
+ demand_empty_rest_of_line ();
|
||||
+ return;
|
||||
+ }
|
||||
}
|
||||
- else
|
||||
- as_bad (_("missing cpu architecture"));
|
||||
+
|
||||
+ if (j == ARRAY_SIZE (cpu_arch))
|
||||
+ as_bad (_("no such architecture: `%s'"), string);
|
||||
+
|
||||
+ *input_line_pointer = e;
|
||||
|
||||
no_cond_jump_promotion = 0;
|
||||
if (*input_line_pointer == ','
|
||||
&& !is_end_of_line[(unsigned char) input_line_pointer[1]])
|
||||
{
|
||||
- char *string;
|
||||
- char e;
|
||||
-
|
||||
++input_line_pointer;
|
||||
- e = get_symbol_name (&string);
|
||||
+ e = get_symbol_name (&s);
|
||||
+ string = s;
|
||||
|
||||
if (strcmp (string, "nojumps") == 0)
|
||||
no_cond_jump_promotion = 1;
|
||||
--
|
||||
2.43.0
|
||||
|
||||
160
i686-AVX10.1-part-3.patch
Normal file
160
i686-AVX10.1-part-3.patch
Normal file
@ -0,0 +1,160 @@
|
||||
diff -rup fred/gas/config/tc-i386.c binutils-2.41/gas/config/tc-i386.c
|
||||
--- fred/gas/config/tc-i386.c 2023-12-07 10:00:21.013005830 +0000
|
||||
+++ binutils-2.41/gas/config/tc-i386.c 2023-12-07 10:00:28.037015037 +0000
|
||||
@@ -1053,8 +1053,8 @@ static const arch_entry cpu_arch[] =
|
||||
SUBARCH (xsavec, XSAVEC, ANY_XSAVEC, false),
|
||||
SUBARCH (xsaves, XSAVES, ANY_XSAVES, false),
|
||||
SUBARCH (aes, AES, ANY_AES, false),
|
||||
- SUBARCH (pclmul, PCLMUL, ANY_PCLMUL, false),
|
||||
- SUBARCH (clmul, PCLMUL, ANY_PCLMUL, true),
|
||||
+ SUBARCH (pclmul, PCLMULQDQ, ANY_PCLMULQDQ, false),
|
||||
+ SUBARCH (clmul, PCLMULQDQ, ANY_PCLMULQDQ, true),
|
||||
SUBARCH (fsgsbase, FSGSBASE, FSGSBASE, false),
|
||||
SUBARCH (rdrnd, RDRND, RDRND, false),
|
||||
SUBARCH (f16c, F16C, ANY_F16C, false),
|
||||
@@ -1861,7 +1861,7 @@ cpu_flags_match (const insn_template *t)
|
||||
|| (sse2avx && !i.prefix[DATA_PREFIX]))
|
||||
&& (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
|
||||
&& (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
|
||||
- && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul))
|
||||
+ && (!x.bitfield.cpupclmulqdq || cpu.bitfield.cpupclmulqdq))
|
||||
match |= CPU_FLAGS_ARCH_MATCH;
|
||||
}
|
||||
else if (x.bitfield.cpuavx512f)
|
||||
diff -rup fred/opcodes/i386-gen.c binutils-2.41/opcodes/i386-gen.c
|
||||
--- fred/opcodes/i386-gen.c 2023-12-07 10:00:22.092007244 +0000
|
||||
+++ binutils-2.41/opcodes/i386-gen.c 2023-12-07 10:00:28.038015039 +0000
|
||||
@@ -79,7 +79,7 @@ static const dependency isa_dependencies
|
||||
{ "AMDFAM10",
|
||||
"K8|FISTTP|SSE4A|ABM|MONITOR" },
|
||||
{ "BDVER1",
|
||||
- "GENERIC64|FISTTP|Rdtscp|MONITOR|CX16|LAHF_SAHF|XOP|ABM|LWP|SVME|AES|PCLMUL|PRFCHW" },
|
||||
+ "GENERIC64|FISTTP|Rdtscp|MONITOR|CX16|LAHF_SAHF|XOP|ABM|LWP|SVME|AES|PCLMULQDQ|PRFCHW" },
|
||||
{ "BDVER2",
|
||||
"BDVER1|FMA|BMI|TBM|F16C" },
|
||||
{ "BDVER3",
|
||||
@@ -87,7 +87,7 @@ static const dependency isa_dependencies
|
||||
{ "BDVER4",
|
||||
"BDVER3|AVX2|Movbe|BMI2|RdRnd|MWAITX" },
|
||||
{ "ZNVER1",
|
||||
- "GENERIC64|FISTTP|Rdtscp|MONITOR|CX16|LAHF_SAHF|AVX2|SSE4A|ABM|SVME|AES|PCLMUL|PRFCHW|FMA|BMI|F16C|Xsaveopt|FSGSBase|Movbe|BMI2|RdRnd|ADX|RdSeed|SMAP|SHA|XSAVEC|XSAVES|ClflushOpt|CLZERO|MWAITX" },
|
||||
+ "GENERIC64|FISTTP|Rdtscp|MONITOR|CX16|LAHF_SAHF|AVX2|SSE4A|ABM|SVME|AES|PCLMULQDQ|PRFCHW|FMA|BMI|F16C|Xsaveopt|FSGSBase|Movbe|BMI2|RdRnd|ADX|RdSeed|SMAP|SHA|XSAVEC|XSAVES|ClflushOpt|CLZERO|MWAITX" },
|
||||
{ "ZNVER2",
|
||||
"ZNVER1|CLWB|RDPID|RDPRU|MCOMMIT|WBNOINVD" },
|
||||
{ "ZNVER3",
|
||||
@@ -97,7 +97,7 @@ static const dependency isa_dependencies
|
||||
{ "BTVER1",
|
||||
"GENERIC64|FISTTP|MONITOR|CX16|LAHF_SAHF|Rdtscp|SSSE3|SSE4A|ABM|PRFCHW|Clflush|FISTTP|SVME" },
|
||||
{ "BTVER2",
|
||||
- "BTVER1|AVX|BMI|F16C|AES|PCLMUL|Movbe|Xsaveopt|PRFCHW" },
|
||||
+ "BTVER1|AVX|BMI|F16C|AES|PCLMULQDQ|Movbe|Xsaveopt|PRFCHW" },
|
||||
{ "286",
|
||||
"186" },
|
||||
{ "386",
|
||||
@@ -132,7 +132,7 @@ static const dependency isa_dependencies
|
||||
"XSAVE" },
|
||||
{ "AES",
|
||||
"SSE2" },
|
||||
- { "PCLMUL",
|
||||
+ { "PCLMULQDQ",
|
||||
"SSE2" },
|
||||
{ "FMA",
|
||||
"AVX" },
|
||||
@@ -307,7 +307,7 @@ static bitfield cpu_flags[] =
|
||||
BITFIELD (Xsave),
|
||||
BITFIELD (Xsaveopt),
|
||||
BITFIELD (AES),
|
||||
- BITFIELD (PCLMUL),
|
||||
+ BITFIELD (PCLMULQDQ),
|
||||
BITFIELD (FMA),
|
||||
BITFIELD (FMA4),
|
||||
BITFIELD (XOP),
|
||||
diff -rup fred/opcodes/i386-init.h binutils-2.41/opcodes/i386-init.h
|
||||
--- fred/opcodes/i386-init.h 2023-12-07 10:00:22.092007244 +0000
|
||||
+++ binutils-2.41/opcodes/i386-init.h 2023-12-07 10:00:51.260045479 +0000
|
||||
@@ -432,7 +432,7 @@
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
-#define CPU_PCLMUL_FLAGS \
|
||||
+#define CPU_PCLMULQDQ_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
@@ -1791,7 +1791,7 @@
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
-#define CPU_ANY_PCLMUL_FLAGS \
|
||||
+#define CPU_ANY_PCLMULQDQ_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
diff -rup fred/opcodes/i386-opc.h binutils-2.41/opcodes/i386-opc.h
|
||||
--- fred/opcodes/i386-opc.h 2023-12-07 10:00:22.093007246 +0000
|
||||
+++ binutils-2.41/opcodes/i386-opc.h 2023-12-07 10:00:28.038015039 +0000
|
||||
@@ -121,8 +121,8 @@ enum
|
||||
CpuXsaveopt,
|
||||
/* AES support required */
|
||||
CpuAES,
|
||||
- /* PCLMUL support required */
|
||||
- CpuPCLMUL,
|
||||
+ /* PCLMULQDQ support required */
|
||||
+ CpuPCLMULQDQ,
|
||||
/* FMA support required */
|
||||
CpuFMA,
|
||||
/* FMA4 support required */
|
||||
@@ -374,7 +374,7 @@ typedef union i386_cpu_flags
|
||||
unsigned int cpuxsave:1;
|
||||
unsigned int cpuxsaveopt:1;
|
||||
unsigned int cpuaes:1;
|
||||
- unsigned int cpupclmul:1;
|
||||
+ unsigned int cpupclmulqdq:1;
|
||||
unsigned int cpufma:1;
|
||||
unsigned int cpufma4:1;
|
||||
unsigned int cpuxop:1;
|
||||
diff -rup fred/opcodes/i386-opc.tbl binutils-2.41/opcodes/i386-opc.tbl
|
||||
--- fred/opcodes/i386-opc.tbl 2023-12-07 10:00:22.093007246 +0000
|
||||
+++ binutils-2.41/opcodes/i386-opc.tbl 2023-12-07 10:00:28.038015039 +0000
|
||||
@@ -1448,15 +1448,15 @@ vaesdeclast, 0x66df, VAES, Modrm|Vex256|
|
||||
vaesenc, 0x66dc, VAES, Modrm|Vex256|Space0F38|VexVVVV|VexWIG|NoSuf, { RegYMM|Unspecified|BaseIndex, RegYMM, RegYMM }
|
||||
vaesenclast, 0x66dd, VAES, Modrm|Vex256|Space0F38|VexVVVV|VexWIG|NoSuf, { RegYMM|Unspecified|BaseIndex, RegYMM, RegYMM }
|
||||
|
||||
-// PCLMUL
|
||||
+// PCLMULQDQ
|
||||
|
||||
<pclmul:cpu:attr, $avx:AVX|:Vex128|VexW0|SSE2AVX|VexVVVV, $sse::>
|
||||
|
||||
-pclmulqdq<pclmul>, 0x660f3a44, <pclmul:cpu>PCLMUL, Modrm|<pclmul:attr>|NoSuf, { Imm8|Imm8S, RegXMM|Unspecified|BaseIndex, RegXMM }
|
||||
-pclmullqlqdq<pclmul>, 0x660f3a44/0x00, <pclmul:cpu>PCLMUL, Modrm|<pclmul:attr>|NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM }
|
||||
-pclmulhqlqdq<pclmul>, 0x660f3a44/0x01, <pclmul:cpu>PCLMUL, Modrm|<pclmul:attr>|NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM }
|
||||
-pclmullqhqdq<pclmul>, 0x660f3a44/0x10, <pclmul:cpu>PCLMUL, Modrm|<pclmul:attr>|NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM }
|
||||
-pclmulhqhqdq<pclmul>, 0x660f3a44/0x11, <pclmul:cpu>PCLMUL, Modrm|<pclmul:attr>|NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM }
|
||||
+pclmulqdq<pclmul>, 0x660f3a44, <pclmul:cpu>PCLMULQDQ, Modrm|<pclmul:attr>|NoSuf, { Imm8|Imm8S, RegXMM|Unspecified|BaseIndex, RegXMM }
|
||||
+pclmullqlqdq<pclmul>, 0x660f3a44/0x00, <pclmul:cpu>PCLMULQDQ, Modrm|<pclmul:attr>|NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM }
|
||||
+pclmulhqlqdq<pclmul>, 0x660f3a44/0x01, <pclmul:cpu>PCLMULQDQ, Modrm|<pclmul:attr>|NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM }
|
||||
+pclmullqhqdq<pclmul>, 0x660f3a44/0x10, <pclmul:cpu>PCLMULQDQ, Modrm|<pclmul:attr>|NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM }
|
||||
+pclmulhqhqdq<pclmul>, 0x660f3a44/0x11, <pclmul:cpu>PCLMULQDQ, Modrm|<pclmul:attr>|NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM }
|
||||
|
||||
// GFNI
|
||||
|
||||
@@ -1771,13 +1771,13 @@ vaesenclast, 0x66dd, AVX|AES, Modrm|Vex|
|
||||
vaesimc, 0x66db, AVX|AES, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM }
|
||||
vaeskeygenassist, 0x66df, AVX|AES, Modrm|Vex|Space0F3A|VexWIG|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM }
|
||||
|
||||
-// PCLMUL + AVX
|
||||
+// PCLMULQDQ + AVX
|
||||
|
||||
-vpclmulqdq, 0x6644, AVX|PCLMUL, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
|
||||
-vpclmullqlqdq, 0x6644/0x00, AVX|PCLMUL, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|NoSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
|
||||
-vpclmulhqlqdq, 0x6644/0x01, AVX|PCLMUL, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|NoSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
|
||||
-vpclmullqhqdq, 0x6644/0x10, AVX|PCLMUL, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|NoSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
|
||||
-vpclmulhqhqdq, 0x6644/0x11, AVX|PCLMUL, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|NoSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
|
||||
+vpclmulqdq, 0x6644, AVX|PCLMULQDQ, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
|
||||
+vpclmullqlqdq, 0x6644/0x00, AVX|PCLMULQDQ, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|NoSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
|
||||
+vpclmulhqlqdq, 0x6644/0x01, AVX|PCLMULQDQ, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|NoSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
|
||||
+vpclmullqhqdq, 0x6644/0x10, AVX|PCLMULQDQ, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|NoSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
|
||||
+vpclmulhqhqdq, 0x6644/0x11, AVX|PCLMULQDQ, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|NoSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
|
||||
|
||||
// GFNI + AVX
|
||||
|
||||
1121
i686-AVX10.1-part-4.patch
Normal file
1121
i686-AVX10.1-part-4.patch
Normal file
File diff suppressed because it is too large
Load Diff
3092
i686-AVX10.1-part-5.patch
Normal file
3092
i686-AVX10.1-part-5.patch
Normal file
File diff suppressed because it is too large
Load Diff
39749
i686-AVX10.1-part-6.patch
Normal file
39749
i686-AVX10.1-part-6.patch
Normal file
File diff suppressed because it is too large
Load Diff
Loading…
x
Reference in New Issue
Block a user