binutils/binutils-2.19.51.0.2-IBM.patch

diff -rcp ../binutils-2.19.51.0.2.15/bfd/elf32-lm32.c ./bfd/elf32-lm32.c
*** ../binutils-2.19.51.0.2.15/bfd/elf32-lm32.c	2009-03-02 14:05:10.000000000 +0000
--- ./bfd/elf32-lm32.c	2009-03-05 12:12:25.000000000 +0000
*************** lm32_elf_relocate_section (bfd *output_b
*** 888,898 ****
            /* It's a global symbol.  */
            bfd_boolean unresolved_reloc;
  	  bfd_boolean warned;
  
  	  RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
  				   r_symndx, symtab_hdr, sym_hashes,
  				   h, sec, relocation,
! 				   unresolved_reloc, warned);
  	  osec = sec;
  	  name = h->root.root.string;
          }
--- 888,899 ----
            /* It's a global symbol.  */
            bfd_boolean unresolved_reloc;
  	  bfd_boolean warned;
+ 	  bfd_boolean ignored;
  
  	  RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
  				   r_symndx, symtab_hdr, sym_hashes,
  				   h, sec, relocation,
! 				   unresolved_reloc, warned, ignored);
  	  osec = sec;
  	  name = h->root.root.string;
          }
diff -rcp ../binutils-2.19.51.0.2.15/bfd/elf32-ppc.c ./bfd/elf32-ppc.c
*** ../binutils-2.19.51.0.2.15/bfd/elf32-ppc.c	2009-03-02 14:05:10.000000000 +0000
--- ./bfd/elf32-ppc.c	2009-03-05 12:20:26.000000000 +0000
***************
*** 1,6 ****
  /* PowerPC-specific support for 32-bit ELF
     Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
!    2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
     Written by Ian Lance Taylor, Cygnus Support.
  
     This file is part of BFD, the Binary File Descriptor library.
--- 1,6 ----
  /* PowerPC-specific support for 32-bit ELF
     Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
!    2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
     Written by Ian Lance Taylor, Cygnus Support.
  
     This file is part of BFD, the Binary File Descriptor library.
*************** ppc_elf_gc_sweep_hook (bfd *abfd,
*** 4301,4307 ****
    return TRUE;
  }
  
! /* Set htab->tls_get_addr and call the generic ELF tls_setup function.  */
  
  asection *
  ppc_elf_tls_setup (bfd *obfd, struct bfd_link_info *info)
--- 4301,4308 ----
    return TRUE;
  }
  
! /* Set plt output section type, htab->tls_get_addr, and call the
!    generic ELF tls_setup function.  */
  
  asection *
  ppc_elf_tls_setup (bfd *obfd, struct bfd_link_info *info)
*************** ppc_elf_tls_setup (bfd *obfd, struct bfd
*** 4322,4327 ****
--- 4323,4365 ----
    return _bfd_elf_tls_setup (obfd, info);
  }
  
+ /* Return TRUE iff REL is a branch reloc with a global symbol matching
+    HASH.  */
+ 
+ static bfd_boolean
+ branch_reloc_hash_match (const bfd *ibfd,
+ 			 const Elf_Internal_Rela *rel,
+ 			 const struct elf_link_hash_entry *hash)
+ {
+   Elf_Internal_Shdr *symtab_hdr = &elf_symtab_hdr (ibfd);
+   enum elf_ppc_reloc_type r_type = ELF32_R_TYPE (rel->r_info);
+   unsigned int r_symndx = ELF32_R_SYM (rel->r_info);
+ 
+   if (r_symndx >= symtab_hdr->sh_info
+       && (r_type == R_PPC_PLTREL24
+ 	  || r_type == R_PPC_LOCAL24PC
+ 	  || r_type == R_PPC_REL14
+ 	  || r_type == R_PPC_REL14_BRTAKEN
+ 	  || r_type == R_PPC_REL14_BRNTAKEN
+ 	  || r_type == R_PPC_REL24
+ 	  || r_type == R_PPC_ADDR24
+ 	  || r_type == R_PPC_ADDR14
+ 	  || r_type == R_PPC_ADDR14_BRTAKEN
+ 	  || r_type == R_PPC_ADDR14_BRNTAKEN))
+     {
+       struct elf_link_hash_entry **sym_hashes = elf_sym_hashes (ibfd);
+       struct elf_link_hash_entry *h;
+ 
+       h = sym_hashes[r_symndx - symtab_hdr->sh_info];
+       while (h->root.type == bfd_link_hash_indirect
+ 	     || h->root.type == bfd_link_hash_warning)
+ 	h = (struct elf_link_hash_entry *) h->root.u.i.link;
+       if (h == hash)
+ 	return TRUE;
+     }
+   return FALSE;
+ }
+ 
  /* Run through all the TLS relocs looking for optimization
     opportunities.  */
  
*************** ppc_elf_tls_optimize (bfd *obfd ATTRIBUT
*** 4449,4483 ****
  		      if (!expecting_tls_get_addr)
  			continue;
  
! 		      if (rel + 1 < relend)
! 			{
! 			  enum elf_ppc_reloc_type r_type2;
! 			  unsigned long r_symndx2;
! 			  struct elf_link_hash_entry *h2;
! 
! 			  /* The next instruction should be a call to
! 			     __tls_get_addr.  Peek at the reloc to be sure.  */
! 			  r_type2 = ELF32_R_TYPE (rel[1].r_info);
! 			  r_symndx2 = ELF32_R_SYM (rel[1].r_info);
! 			  if (r_symndx2 >= symtab_hdr->sh_info
! 			      && (r_type2 == R_PPC_REL14
! 				  || r_type2 == R_PPC_REL14_BRTAKEN
! 				  || r_type2 == R_PPC_REL14_BRNTAKEN
! 				  || r_type2 == R_PPC_REL24
! 				  || r_type2 == R_PPC_PLTREL24))
! 			    {
! 			      struct elf_link_hash_entry **sym_hashes;
! 
! 			      sym_hashes = elf_sym_hashes (ibfd);
! 			      h2 = sym_hashes[r_symndx2 - symtab_hdr->sh_info];
! 			      while (h2->root.type == bfd_link_hash_indirect
! 				     || h2->root.type == bfd_link_hash_warning)
! 				h2 = ((struct elf_link_hash_entry *)
! 				      h2->root.u.i.link);
! 			      if (h2 == htab->tls_get_addr)
! 				continue;
! 			    }
! 			}
  
  		      /* Uh oh, we didn't find the expected call.  We
  			 could just mark this symbol to exclude it
--- 4487,4496 ----
  		      if (!expecting_tls_get_addr)
  			continue;
  
! 		      if (rel + 1 < relend
! 			  && branch_reloc_hash_match (ibfd, rel + 1,
! 						      htab->tls_get_addr))
! 			continue;
  
  		      /* Uh oh, we didn't find the expected call.  We
  			 could just mark this symbol to exclude it
*************** ppc_elf_relocate_section (bfd *output_bf
*** 6346,6367 ****
  	case R_PPC_GOT_TLSLD16_LO:
  	  if (tls_mask != 0 && (tls_mask & TLS_LD) == 0)
  	    {
! 	      bfd_vma insn1, insn2;
  	      bfd_vma offset;
  
  	    tls_ldgd_opt:
  	      offset = rel[1].r_offset;
- 	      insn1 = bfd_get_32 (output_bfd,
- 				  contents + rel->r_offset - d_offset);
  	      if ((tls_mask & tls_gd) != 0)
  		{
  		  /* IE */
  		  insn1 &= (1 << 26) - 1;
  		  insn1 |= 32 << 26;	/* lwz */
  		  insn2 = 0x7c631214;	/* add 3,3,2 */
  		  rel[1].r_info
  		    = ELF32_R_INFO (ELF32_R_SYM (rel[1].r_info), R_PPC_NONE);
- 		  rel[1].r_addend = 0;
  		  r_type = (((r_type - (R_PPC_GOT_TLSGD16 & 3)) & 3)
  			    + R_PPC_GOT_TPREL16);
  		  rel->r_info = ELF32_R_INFO (r_symndx, r_type);
--- 6359,6379 ----
  	case R_PPC_GOT_TLSLD16_LO:
  	  if (tls_mask != 0 && (tls_mask & TLS_LD) == 0)
  	    {
! 	      unsigned int insn1, insn2;
  	      bfd_vma offset;
  
  	    tls_ldgd_opt:
  	      offset = rel[1].r_offset;
  	      if ((tls_mask & tls_gd) != 0)
  		{
  		  /* IE */
+ 		  insn1 = bfd_get_32 (output_bfd,
+ 				      contents + rel->r_offset - d_offset);
  		  insn1 &= (1 << 26) - 1;
  		  insn1 |= 32 << 26;	/* lwz */
  		  insn2 = 0x7c631214;	/* add 3,3,2 */
  		  rel[1].r_info
  		    = ELF32_R_INFO (ELF32_R_SYM (rel[1].r_info), R_PPC_NONE);
  		  r_type = (((r_type - (R_PPC_GOT_TLSGD16 & 3)) & 3)
  			    + R_PPC_GOT_TPREL16);
  		  rel->r_info = ELF32_R_INFO (r_symndx, r_type);
diff -rcp ../binutils-2.19.51.0.2.15/bfd/elf64-ppc.c ./bfd/elf64-ppc.c
*** ../binutils-2.19.51.0.2.15/bfd/elf64-ppc.c	2009-03-02 14:05:10.000000000 +0000
--- ./bfd/elf64-ppc.c	2009-03-05 12:20:26.000000000 +0000
***************
*** 1,6 ****
  /* PowerPC64-specific support for 64-bit ELF.
!    Copyright 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
!    Free Software Foundation, Inc.
     Written by Linus Nordberg, Swox AB <info@swox.com>,
     based on elf32-ppc.c by Ian Lance Taylor.
     Largely rewritten by Alan Modra <amodra@bigpond.net.au>
--- 1,6 ----
  /* PowerPC64-specific support for 64-bit ELF.
!    Copyright 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008,
!    2009 Free Software Foundation, Inc.
     Written by Linus Nordberg, Swox AB <info@swox.com>,
     based on elf32-ppc.c by Ian Lance Taylor.
     Largely rewritten by Alan Modra <amodra@bigpond.net.au>
*************** struct _ppc64_elf_section_data
*** 2608,2616 ****
        long *adjust;
      } opd;
  
!     /* An array for toc sections, indexed by offset/8.
!        Specifies the relocation symbol index used at a given toc offset.  */
!     unsigned *t_symndx;
    } u;
  
    enum _ppc64_sec_type sec_type:2;
--- 2608,2622 ----
        long *adjust;
      } opd;
  
!     /* An array for toc sections, indexed by offset/8.  */
!     struct _toc_sec_data
!     {
!       /* Specifies the relocation symbol index used at a given toc offset.  */
!       unsigned *symndx;
! 
!       /* And the relocation addend.  */
!       bfd_vma *add;
!     } toc;
    } u;
  
    enum _ppc64_sec_type sec_type:2;
*************** ppc64_elf_check_relocs (bfd *abfd, struc
*** 4578,4583 ****
--- 4584,4590 ----
    const Elf_Internal_Rela *rel_end;
    asection *sreloc;
    asection **opd_sym_map;
+   struct elf_link_hash_entry *tga, *dottga;
  
    if (info->relocatable)
      return TRUE;
*************** ppc64_elf_check_relocs (bfd *abfd, struc
*** 4594,4599 ****
--- 4601,4610 ----
    BFD_ASSERT (is_ppc64_elf (abfd));
  
    htab = ppc_hash_table (info);
+   tga = elf_link_hash_lookup (&htab->elf, "__tls_get_addr",
+ 			      FALSE, FALSE, TRUE);
+   dottga = elf_link_hash_lookup (&htab->elf, ".__tls_get_addr",
+ 				 FALSE, FALSE, TRUE);
    symtab_hdr = &elf_symtab_hdr (abfd);
  
    sym_hashes = elf_sym_hashes (abfd);
*************** ppc64_elf_check_relocs (bfd *abfd, struc
*** 4829,4853 ****
  	      if (!update_plt_info (abfd, (struct ppc_link_hash_entry *) h,
  				    rel->r_addend))
  		return FALSE;
! 	      if (h == &htab->tls_get_addr->elf
! 		  || h == &htab->tls_get_addr_fd->elf)
  		sec->has_tls_reloc = 1;
- 	      else if (htab->tls_get_addr == NULL
- 		       && CONST_STRNEQ (h->root.root.string, ".__tls_get_addr")
- 		       && (h->root.root.string[15] == 0
- 			   || h->root.root.string[15] == '@'))
- 		{
- 		  htab->tls_get_addr = (struct ppc_link_hash_entry *) h;
- 		  sec->has_tls_reloc = 1;
- 		}
- 	      else if (htab->tls_get_addr_fd == NULL
- 		       && CONST_STRNEQ (h->root.root.string, "__tls_get_addr")
- 		       && (h->root.root.string[14] == 0
- 			   || h->root.root.string[14] == '@'))
- 		{
- 		  htab->tls_get_addr_fd = (struct ppc_link_hash_entry *) h;
- 		  sec->has_tls_reloc = 1;
- 		}
  	    }
  	  break;
  
--- 4840,4847 ----
  	      if (!update_plt_info (abfd, (struct ppc_link_hash_entry *) h,
  				    rel->r_addend))
  		return FALSE;
! 	      if (h == tga || h == dottga)
  		sec->has_tls_reloc = 1;
  	    }
  	  break;
  
*************** ppc64_elf_check_relocs (bfd *abfd, struc
*** 4891,4913 ****
  	  ppc64_sec = ppc64_elf_section_data (sec);
  	  if (ppc64_sec->sec_type != sec_toc)
  	    {
  	      /* One extra to simplify get_tls_mask.  */
! 	      bfd_size_type amt = sec->size * sizeof (unsigned) / 8 + 1;
! 	      ppc64_sec->u.t_symndx = bfd_zalloc (abfd, amt);
! 	      if (ppc64_sec->u.t_symndx == NULL)
  		return FALSE;
  	      BFD_ASSERT (ppc64_sec->sec_type == sec_normal);
  	      ppc64_sec->sec_type = sec_toc;
  	    }
  	  BFD_ASSERT (rel->r_offset % 8 == 0);
! 	  ppc64_sec->u.t_symndx[rel->r_offset / 8] = r_symndx;
  
  	  /* Mark the second slot of a GD or LD entry.
  	     -1 to indicate GD and -2 to indicate LD.  */
  	  if (tls_type == (TLS_EXPLICIT | TLS_TLS | TLS_GD))
! 	    ppc64_sec->u.t_symndx[rel->r_offset / 8 + 1] = -1;
  	  else if (tls_type == (TLS_EXPLICIT | TLS_TLS | TLS_LD))
! 	    ppc64_sec->u.t_symndx[rel->r_offset / 8 + 1] = -2;
  	  goto dodyn;
  
  	case R_PPC64_TPREL16:
--- 4885,4914 ----
  	  ppc64_sec = ppc64_elf_section_data (sec);
  	  if (ppc64_sec->sec_type != sec_toc)
  	    {
+ 	      bfd_size_type amt;
+ 
  	      /* One extra to simplify get_tls_mask.  */
! 	      amt = sec->size * sizeof (unsigned) / 8 + sizeof (unsigned);
! 	      ppc64_sec->u.toc.symndx = bfd_zalloc (abfd, amt);
! 	      if (ppc64_sec->u.toc.symndx == NULL)
! 		return FALSE;
! 	      amt = sec->size * sizeof (bfd_vma) / 8;
! 	      ppc64_sec->u.toc.add = bfd_zalloc (abfd, amt);
! 	      if (ppc64_sec->u.toc.add == NULL)
  		return FALSE;
  	      BFD_ASSERT (ppc64_sec->sec_type == sec_normal);
  	      ppc64_sec->sec_type = sec_toc;
  	    }
  	  BFD_ASSERT (rel->r_offset % 8 == 0);
! 	  ppc64_sec->u.toc.symndx[rel->r_offset / 8] = r_symndx;
! 	  ppc64_sec->u.toc.add[rel->r_offset / 8] = rel->r_addend;
  
  	  /* Mark the second slot of a GD or LD entry.
  	     -1 to indicate GD and -2 to indicate LD.  */
  	  if (tls_type == (TLS_EXPLICIT | TLS_TLS | TLS_GD))
! 	    ppc64_sec->u.toc.symndx[rel->r_offset / 8 + 1] = -1;
  	  else if (tls_type == (TLS_EXPLICIT | TLS_TLS | TLS_LD))
! 	    ppc64_sec->u.toc.symndx[rel->r_offset / 8 + 1] = -2;
  	  goto dodyn;
  
  	case R_PPC64_TPREL16:
*************** get_sym_h (struct elf_link_hash_entry **
*** 6226,6234 ****
     type suitable for optimization, and 1 otherwise.  */
  
  static int
! get_tls_mask (char **tls_maskp, unsigned long *toc_symndx,
  	      Elf_Internal_Sym **locsymsp,
! 	      const Elf_Internal_Rela *rel, bfd *ibfd)
  {
    unsigned long r_symndx;
    int next_r;
--- 6227,6238 ----
     type suitable for optimization, and 1 otherwise.  */
  
  static int
! get_tls_mask (char **tls_maskp,
! 	      unsigned long *toc_symndx,
! 	      bfd_vma *toc_addend,
  	      Elf_Internal_Sym **locsymsp,
! 	      const Elf_Internal_Rela *rel,
! 	      bfd *ibfd)
  {
    unsigned long r_symndx;
    int next_r;
*************** get_tls_mask (char **tls_maskp, unsigned
*** 6256,6267 ****
      off = sym->st_value;
    off += rel->r_addend;
    BFD_ASSERT (off % 8 == 0);
!   r_symndx = ppc64_elf_section_data (sec)->u.t_symndx[off / 8];
!   next_r = ppc64_elf_section_data (sec)->u.t_symndx[off / 8 + 1];
!   if (!get_sym_h (&h, &sym, &sec, tls_maskp, locsymsp, r_symndx, ibfd))
!     return 0;
    if (toc_symndx != NULL)
      *toc_symndx = r_symndx;
    if ((h == NULL
         || ((h->root.type == bfd_link_hash_defined
  	    || h->root.type == bfd_link_hash_defweak)
--- 6260,6273 ----
      off = sym->st_value;
    off += rel->r_addend;
    BFD_ASSERT (off % 8 == 0);
!   r_symndx = ppc64_elf_section_data (sec)->u.toc.symndx[off / 8];
!   next_r = ppc64_elf_section_data (sec)->u.toc.symndx[off / 8 + 1];
    if (toc_symndx != NULL)
      *toc_symndx = r_symndx;
+   if (toc_addend != NULL)
+     *toc_addend = ppc64_elf_section_data (sec)->u.toc.add[off / 8];
+   if (!get_sym_h (&h, &sym, &sec, tls_maskp, locsymsp, r_symndx, ibfd))
+     return 0;
    if ((h == NULL
         || ((h->root.type == bfd_link_hash_defined
  	    || h->root.type == bfd_link_hash_defweak)
*************** ppc64_elf_tls_setup (bfd *obfd, struct b
*** 6866,6901 ****
    struct ppc_link_hash_table *htab;
  
    htab = ppc_hash_table (info);
!   if (htab->tls_get_addr != NULL)
!     {
!       struct ppc_link_hash_entry *h = htab->tls_get_addr;
! 
!       while (h->elf.root.type == bfd_link_hash_indirect
! 	     || h->elf.root.type == bfd_link_hash_warning)
! 	h = (struct ppc_link_hash_entry *) h->elf.root.u.i.link;
  
!       htab->tls_get_addr = h;
  
!       if (htab->tls_get_addr_fd == NULL
! 	  && h->oh != NULL
! 	  && h->oh->is_func_descriptor
! 	  && (h->oh->elf.root.type == bfd_link_hash_defined
! 	      || h->oh->elf.root.type == bfd_link_hash_defweak))
! 	htab->tls_get_addr_fd = h->oh;
!     }
  
!   if (htab->tls_get_addr_fd != NULL)
      {
!       struct ppc_link_hash_entry *h = htab->tls_get_addr_fd;
! 
!       while (h->elf.root.type == bfd_link_hash_indirect
! 	     || h->elf.root.type == bfd_link_hash_warning)
! 	h = (struct ppc_link_hash_entry *) h->elf.root.u.i.link;
  
!       htab->tls_get_addr_fd = h;
      }
! 
!   return _bfd_elf_tls_setup (obfd, info);
  }
  
  /* Run through all the TLS relocs looking for optimization
--- 6872,6920 ----
    struct ppc_link_hash_table *htab;
  
    htab = ppc_hash_table (info);
!   htab->tls_get_addr = ((struct ppc_link_hash_entry *)
! 			elf_link_hash_lookup (&htab->elf, ".__tls_get_addr",
! 					      FALSE, FALSE, TRUE));
!   htab->tls_get_addr_fd = ((struct ppc_link_hash_entry *)
! 			   elf_link_hash_lookup (&htab->elf, "__tls_get_addr",
! 						 FALSE, FALSE, TRUE));
!   return _bfd_elf_tls_setup (obfd, info);
! }
  
! /* Return TRUE iff REL is a branch reloc with a global symbol matching
!    HASH1 or HASH2.  */
  
! static bfd_boolean
! branch_reloc_hash_match (const bfd *ibfd,
! 			 const Elf_Internal_Rela *rel,
! 			 const struct ppc_link_hash_entry *hash1,
! 			 const struct ppc_link_hash_entry *hash2)
! {
!   Elf_Internal_Shdr *symtab_hdr = &elf_symtab_hdr (ibfd);
!   enum elf_ppc64_reloc_type r_type = ELF64_R_TYPE (rel->r_info);
!   unsigned int r_symndx = ELF64_R_SYM (rel->r_info);
  
!   if (r_symndx >= symtab_hdr->sh_info
!       && (r_type == R_PPC64_REL24
! 	  || r_type == R_PPC64_REL14
! 	  || r_type == R_PPC64_REL14_BRTAKEN
! 	  || r_type == R_PPC64_REL14_BRNTAKEN
! 	  || r_type == R_PPC64_ADDR24
! 	  || r_type == R_PPC64_ADDR14
! 	  || r_type == R_PPC64_ADDR14_BRTAKEN
! 	  || r_type == R_PPC64_ADDR14_BRNTAKEN))
      {
!       struct elf_link_hash_entry **sym_hashes = elf_sym_hashes (ibfd);
!       struct elf_link_hash_entry *h;
  
!       h = sym_hashes[r_symndx - symtab_hdr->sh_info];
!       while (h->root.type == bfd_link_hash_indirect
! 	     || h->root.type == bfd_link_hash_warning)
! 	h = (struct elf_link_hash_entry *) h->root.u.i.link;
!       if (h == &hash1->elf || h == &hash2->elf)
! 	return TRUE;
      }
!   return FALSE;
  }
  
  /* Run through all the TLS relocs looking for optimization
*************** ppc64_elf_tls_optimize (bfd *obfd ATTRIB
*** 7141,7195 ****
  		      if (!expecting_tls_get_addr)
  			continue;
  
! 		      if (rel + 1 < relend)
  			{
! 			  Elf_Internal_Shdr *symtab_hdr;
! 			  enum elf_ppc64_reloc_type r_type2;
! 			  unsigned long r_symndx2;
! 			  struct elf_link_hash_entry *h2;
! 
! 			  symtab_hdr = &elf_symtab_hdr (ibfd);
! 
! 			  /* The next instruction should be a call to
! 			     __tls_get_addr.  Peek at the reloc to be sure.  */
! 			  r_type2 = ELF64_R_TYPE (rel[1].r_info);
! 			  r_symndx2 = ELF64_R_SYM (rel[1].r_info);
! 			  if (r_symndx2 >= symtab_hdr->sh_info
! 			      && (r_type2 == R_PPC64_REL14
! 				  || r_type2 == R_PPC64_REL14_BRTAKEN
! 				  || r_type2 == R_PPC64_REL14_BRNTAKEN
! 				  || r_type2 == R_PPC64_REL24))
  			    {
! 			      struct elf_link_hash_entry **sym_hashes;
! 
! 			      sym_hashes = elf_sym_hashes (ibfd);
! 
! 			      h2 = sym_hashes[r_symndx2 - symtab_hdr->sh_info];
! 			      while (h2->root.type == bfd_link_hash_indirect
! 				     || h2->root.type == bfd_link_hash_warning)
! 				h2 = ((struct elf_link_hash_entry *)
! 				      h2->root.u.i.link);
! 			      if (h2 != NULL
! 				  && (h2 == &htab->tls_get_addr->elf
! 				      || h2 == &htab->tls_get_addr_fd->elf))
! 				{
! 				  if (expecting_tls_get_addr == 2)
! 				    {
! 				      /* Check for toc tls entries.  */
! 				      char *toc_tls;
! 				      int retval;
! 
! 				      retval = get_tls_mask (&toc_tls, NULL,
! 							     &locsyms,
! 							     rel, ibfd);
! 				      if (retval == 0)
! 					goto err_free_rel;
! 				      if (retval > 1 && toc_tls != NULL)
! 					toc_ref[toc_ref_index] = 1;
! 				    }
! 				  continue;
! 				}
  			    }
  			}
  
  		      if (expecting_tls_get_addr != 1)
--- 7160,7185 ----
  		      if (!expecting_tls_get_addr)
  			continue;
  
! 		      if (rel + 1 < relend
! 			  && branch_reloc_hash_match (ibfd, rel + 1,
! 						      htab->tls_get_addr,
! 						      htab->tls_get_addr_fd))
  			{
! 			  if (expecting_tls_get_addr == 2)
  			    {
! 			      /* Check for toc tls entries.  */
! 			      char *toc_tls;
! 			      int retval;
! 
! 			      retval = get_tls_mask (&toc_tls, NULL, NULL,
! 						     &locsyms,
! 						     rel, ibfd);
! 			      if (retval == 0)
! 				goto err_free_rel;
! 			      if (retval > 1 && toc_tls != NULL)
! 				toc_ref[toc_ref_index] = 1;
  			    }
+ 			  continue;
  			}
  
  		      if (expecting_tls_get_addr != 1)
*************** ppc64_elf_size_stubs (bfd *output_bfd,
*** 9712,9718 ****
  		      /* Get tls info.  */
  		      char *tls_mask;
  
! 		      if (!get_tls_mask (&tls_mask, NULL, &local_syms,
  					 irela - 1, input_bfd))
  			goto error_ret_free_internal;
  		      if (*tls_mask != 0)
--- 9702,9708 ----
  		      /* Get tls info.  */
  		      char *tls_mask;
  
! 		      if (!get_tls_mask (&tls_mask, NULL, NULL, &local_syms,
  					 irela - 1, input_bfd))
  			goto error_ret_free_internal;
  		      if (*tls_mask != 0)
*************** ppc64_elf_relocate_section (bfd *output_
*** 10204,10209 ****
--- 10194,10200 ----
        struct ppc_link_hash_entry *fdh;
        const char *sym_name;
        unsigned long r_symndx, toc_symndx;
+       bfd_vma toc_addend;
        char tls_mask, tls_gd, tls_type;
        char sym_type;
        bfd_vma relocation;
*************** ppc64_elf_relocate_section (bfd *output_
*** 10314,10321 ****
  	      /* Check for toc tls entries.  */
  	      char *toc_tls;
  
! 	      if (!get_tls_mask (&toc_tls, &toc_symndx, &local_syms,
! 				 rel, input_bfd))
  		return FALSE;
  
  	      if (toc_tls)
--- 10305,10312 ----
  	      /* Check for toc tls entries.  */
  	      char *toc_tls;
  
! 	      if (!get_tls_mask (&toc_tls, &toc_symndx, &toc_addend,
! 				 &local_syms, rel, input_bfd))
  		return FALSE;
  
  	      if (toc_tls)
*************** ppc64_elf_relocate_section (bfd *output_
*** 10377,10384 ****
  	    char *toc_tls;
  	    int retval;
  
! 	    retval = get_tls_mask (&toc_tls, &toc_symndx, &local_syms,
! 				   rel, input_bfd);
  	    if (retval == 0)
  	      return FALSE;
  
--- 10368,10375 ----
  	    char *toc_tls;
  	    int retval;
  
! 	    retval = get_tls_mask (&toc_tls, &toc_symndx, &toc_addend,
! 				   &local_syms, rel, input_bfd);
  	    if (retval == 0)
  	      return FALSE;
  
*************** ppc64_elf_relocate_section (bfd *output_
*** 10426,10431 ****
--- 10417,10423 ----
  	      if (toc_symndx != 0)
  		{
  		  rel->r_info = ELF64_R_INFO (toc_symndx, r_type);
+ 		  rel->r_addend = toc_addend;
  		  /* We changed the symbol.  Start over in order to
  		     get h, sym, sec etc. right.  */
  		  rel--;
*************** ppc64_elf_relocate_section (bfd *output_
*** 10479,10484 ****
--- 10471,10477 ----
  	      if (toc_symndx != 0)
  		{
  		  rel->r_info = ELF64_R_INFO (toc_symndx, r_type);
+ 		  rel->r_addend = toc_addend;
  		  /* We changed the symbol.  Start over in order to
  		     get h, sym, sec etc. right.  */
  		  rel--;
*************** ppc64_elf_relocate_section (bfd *output_
*** 10525,10544 ****
  	case R_PPC64_GOT_TLSLD16_LO:
  	  if (tls_mask != 0 && (tls_mask & TLS_LD) == 0)
  	    {
! 	      bfd_vma insn1, insn2, insn3;
  	      bfd_vma offset;
  
  	    tls_ldgd_opt:
  	      /* We know that the next reloc is on a tls_get_addr
  		 call, since ppc64_elf_tls_optimize checks this.  */
  	      offset = rel[1].r_offset;
- 	      insn1 = bfd_get_32 (output_bfd,
- 				  contents + rel->r_offset - d_offset);
- 	      insn3 = bfd_get_32 (output_bfd,
- 				  contents + offset + 4);
  	      if ((tls_mask & tls_gd) != 0)
  		{
  		  /* IE */
  		  insn1 &= (1 << 26) - (1 << 2);
  		  insn1 |= 58 << 26;	/* ld */
  		  insn2 = 0x7c636a14;	/* add 3,3,13 */
--- 10518,10535 ----
  	case R_PPC64_GOT_TLSLD16_LO:
  	  if (tls_mask != 0 && (tls_mask & TLS_LD) == 0)
  	    {
! 	      unsigned int insn1, insn2, insn3;
  	      bfd_vma offset;
  
  	    tls_ldgd_opt:
  	      /* We know that the next reloc is on a tls_get_addr
  		 call, since ppc64_elf_tls_optimize checks this.  */
  	      offset = rel[1].r_offset;
  	      if ((tls_mask & tls_gd) != 0)
  		{
  		  /* IE */
+ 		  insn1 = bfd_get_32 (output_bfd,
+ 				      contents + rel->r_offset - d_offset);
  		  insn1 &= (1 << 26) - (1 << 2);
  		  insn1 |= 58 << 26;	/* ld */
  		  insn2 = 0x7c636a14;	/* add 3,3,13 */
*************** ppc64_elf_relocate_section (bfd *output_
*** 10573,10600 ****
  			rel->r_addend -= (local_syms[r_symndx].st_value
  					  + sec->output_offset
  					  + sec->output_section->vma);
- 		      rel[1].r_addend = rel->r_addend;
  		    }
  		  else if (toc_symndx != 0)
! 		    r_symndx = toc_symndx;
  		  r_type = R_PPC64_TPREL16_HA;
  		  rel->r_info = ELF64_R_INFO (r_symndx, r_type);
  		  rel[1].r_info = ELF64_R_INFO (r_symndx,
  						R_PPC64_TPREL16_LO);
  		  rel[1].r_offset += d_offset;
  		}
  	      if (insn3 == NOP
  		  || insn3 == CROR_151515 || insn3 == CROR_313131)
  		{
- 		  insn3 = insn2;
- 		  insn2 = NOP;
  		  rel[1].r_offset += 4;
  		}
- 	      bfd_put_32 (output_bfd, insn1,
- 			  contents + rel->r_offset - d_offset);
  	      bfd_put_32 (output_bfd, insn2, contents + offset);
! 	      bfd_put_32 (output_bfd, insn3, contents + offset + 4);
! 	      if (tls_gd == 0 || toc_symndx != 0)
  		{
  		  /* We changed the symbol.  Start over in order
  		     to get h, sym, sec etc. right.  */
--- 10564,10596 ----
  			rel->r_addend -= (local_syms[r_symndx].st_value
  					  + sec->output_offset
  					  + sec->output_section->vma);
  		    }
  		  else if (toc_symndx != 0)
! 		    {
! 		      r_symndx = toc_symndx;
! 		      rel->r_addend = toc_addend;
! 		    }
  		  r_type = R_PPC64_TPREL16_HA;
  		  rel->r_info = ELF64_R_INFO (r_symndx, r_type);
  		  rel[1].r_info = ELF64_R_INFO (r_symndx,
  						R_PPC64_TPREL16_LO);
  		  rel[1].r_offset += d_offset;
+ 		  rel[1].r_addend = rel->r_addend;
  		}
+ 	      bfd_put_32 (output_bfd, insn1,
+ 			  contents + rel->r_offset - d_offset);
+ 	      insn3 = bfd_get_32 (output_bfd,
+ 				  contents + offset + 4);
  	      if (insn3 == NOP
  		  || insn3 == CROR_151515 || insn3 == CROR_313131)
  		{
  		  rel[1].r_offset += 4;
+ 		  bfd_put_32 (output_bfd, insn2, contents + offset + 4);
+ 		  insn2 = NOP;
  		}
  	      bfd_put_32 (output_bfd, insn2, contents + offset);
! 	      if ((tls_mask & tls_gd) == 0
! 		  && (tls_gd == 0 || toc_symndx != 0))
  		{
  		  /* We changed the symbol.  Start over in order
  		     to get h, sym, sec etc. right.  */
*************** ppc64_elf_relocate_section (bfd *output_
*** 10971,10977 ****
  
  		*offp = off | 1;
  		if ((info->shared || indx != 0)
! 		    && (h == NULL
  			|| ELF_ST_VISIBILITY (h->elf.other) == STV_DEFAULT
  			|| h->elf.root.type != bfd_link_hash_undefweak))
  		  {
--- 10967,10974 ----
  
  		*offp = off | 1;
  		if ((info->shared || indx != 0)
! 		    && (offp == &ppc64_tlsld_got (input_bfd)->offset
! 			|| h == NULL
  			|| ELF_ST_VISIBILITY (h->elf.other) == STV_DEFAULT
  			|| h->elf.root.type != bfd_link_hash_undefweak))
  		  {
diff -rcp ../binutils-2.19.51.0.2.15/gas/config/tc-ppc.c ./gas/config/tc-ppc.c
*** ../binutils-2.19.51.0.2.15/gas/config/tc-ppc.c	2009-03-02 14:05:00.000000000 +0000
--- ./gas/config/tc-ppc.c	2009-03-05 12:20:26.000000000 +0000
*************** static const struct pd_reg pre_defined_r
*** 358,366 ****
--- 358,399 ----
    { "f.3", 3 },
    { "f.30", 30 },
    { "f.31", 31 },
+ 
+   { "f.32", 32 },    /* Extended floating point scalar registers (ISA 2.06).  */
+   { "f.33", 33 },
+   { "f.34", 34 },
+   { "f.35", 35 },
+   { "f.36", 36 },
+   { "f.37", 37 },
+   { "f.38", 38 },
+   { "f.39", 39 },
    { "f.4", 4 },
+   { "f.40", 40 },
+   { "f.41", 41 },
+   { "f.42", 42 },
+   { "f.43", 43 },
+   { "f.44", 44 },
+   { "f.45", 45 },
+   { "f.46", 46 },
+   { "f.47", 47 },
+   { "f.48", 48 },
+   { "f.49", 49 },
    { "f.5", 5 },
+   { "f.50", 50 },
+   { "f.51", 51 },
+   { "f.52", 52 },
+   { "f.53", 53 },
+   { "f.54", 54 },
+   { "f.55", 55 },
+   { "f.56", 56 },
+   { "f.57", 57 },
+   { "f.58", 58 },
+   { "f.59", 59 },
    { "f.6", 6 },
+   { "f.60", 60 },
+   { "f.61", 61 },
+   { "f.62", 62 },
+   { "f.63", 63 },
    { "f.7", 7 },
    { "f.8", 8 },
    { "f.9", 9 },
*************** static const struct pd_reg pre_defined_r
*** 391,399 ****
--- 424,465 ----
    { "f3", 3 },
    { "f30", 30 },
    { "f31", 31 },
+ 
+   { "f32", 32 },    /* Extended floating point scalar registers (ISA 2.06).  */
+   { "f33", 33 },
+   { "f34", 34 },
+   { "f35", 35 },
+   { "f36", 36 },
+   { "f37", 37 },
+   { "f38", 38 },
+   { "f39", 39 },
    { "f4", 4 },
+   { "f40", 40 },
+   { "f41", 41 },
+   { "f42", 42 },
+   { "f43", 43 },
+   { "f44", 44 },
+   { "f45", 45 },
+   { "f46", 46 },
+   { "f47", 47 },
+   { "f48", 48 },
+   { "f49", 49 },
    { "f5", 5 },
+   { "f50", 50 },
+   { "f51", 51 },
+   { "f52", 52 },
+   { "f53", 53 },
+   { "f54", 54 },
+   { "f55", 55 },
+   { "f56", 56 },
+   { "f57", 57 },
+   { "f58", 58 },
+   { "f59", 59 },
    { "f6", 6 },
+   { "f60", 60 },
+   { "f61", 61 },
+   { "f62", 62 },
+   { "f63", 63 },
    { "f7", 7 },
    { "f8", 8 },
    { "f9", 9 },
*************** static const struct pd_reg pre_defined_r
*** 501,507 ****
    { "srr0", 26 }, /* Machine Status Save/Restore Register 0 */
    { "srr1", 27 }, /* Machine Status Save/Restore Register 1 */
  
!   { "v.0", 0 },     /* Vector registers */
    { "v.1", 1 },
    { "v.10", 10 },
    { "v.11", 11 },
--- 567,573 ----
    { "srr0", 26 }, /* Machine Status Save/Restore Register 0 */
    { "srr1", 27 }, /* Machine Status Save/Restore Register 1 */
  
!   { "v.0", 0 },     /* Vector (Altivec/VMX) registers */
    { "v.1", 1 },
    { "v.10", 10 },
    { "v.11", 11 },
*************** static const struct pd_reg pre_defined_r
*** 567,572 ****
--- 633,768 ----
    { "v8", 8 },
    { "v9", 9 },
  
+   { "vs.0", 0 },     /* Vector Scalar (VSX) registers (ISA 2.06).  */
+   { "vs.1", 1 },
+   { "vs.10", 10 },
+   { "vs.11", 11 },
+   { "vs.12", 12 },
+   { "vs.13", 13 },
+   { "vs.14", 14 },
+   { "vs.15", 15 },
+   { "vs.16", 16 },
+   { "vs.17", 17 },
+   { "vs.18", 18 },
+   { "vs.19", 19 },
+   { "vs.2", 2 },
+   { "vs.20", 20 },
+   { "vs.21", 21 },
+   { "vs.22", 22 },
+   { "vs.23", 23 },
+   { "vs.24", 24 },
+   { "vs.25", 25 },
+   { "vs.26", 26 },
+   { "vs.27", 27 },
+   { "vs.28", 28 },
+   { "vs.29", 29 },
+   { "vs.3", 3 },
+   { "vs.30", 30 },
+   { "vs.31", 31 },
+   { "vs.32", 32 },
+   { "vs.33", 33 },
+   { "vs.34", 34 },
+   { "vs.35", 35 },
+   { "vs.36", 36 },
+   { "vs.37", 37 },
+   { "vs.38", 38 },
+   { "vs.39", 39 },
+   { "vs.4", 4 },
+   { "vs.40", 40 },
+   { "vs.41", 41 },
+   { "vs.42", 42 },
+   { "vs.43", 43 },
+   { "vs.44", 44 },
+   { "vs.45", 45 },
+   { "vs.46", 46 },
+   { "vs.47", 47 },
+   { "vs.48", 48 },
+   { "vs.49", 49 },
+   { "vs.5", 5 },
+   { "vs.50", 50 },
+   { "vs.51", 51 },
+   { "vs.52", 52 },
+   { "vs.53", 53 },
+   { "vs.54", 54 },
+   { "vs.55", 55 },
+   { "vs.56", 56 },
+   { "vs.57", 57 },
+   { "vs.58", 58 },
+   { "vs.59", 59 },
+   { "vs.6", 6 },
+   { "vs.60", 60 },
+   { "vs.61", 61 },
+   { "vs.62", 62 },
+   { "vs.63", 63 },
+   { "vs.7", 7 },
+   { "vs.8", 8 },
+   { "vs.9", 9 },
+ 
+   { "vs0", 0 },
+   { "vs1", 1 },
+   { "vs10", 10 },
+   { "vs11", 11 },
+   { "vs12", 12 },
+   { "vs13", 13 },
+   { "vs14", 14 },
+   { "vs15", 15 },
+   { "vs16", 16 },
+   { "vs17", 17 },
+   { "vs18", 18 },
+   { "vs19", 19 },
+   { "vs2", 2 },
+   { "vs20", 20 },
+   { "vs21", 21 },
+   { "vs22", 22 },
+   { "vs23", 23 },
+   { "vs24", 24 },
+   { "vs25", 25 },
+   { "vs26", 26 },
+   { "vs27", 27 },
+   { "vs28", 28 },
+   { "vs29", 29 },
+   { "vs3", 3 },
+   { "vs30", 30 },
+   { "vs31", 31 },
+   { "vs32", 32 },
+   { "vs33", 33 },
+   { "vs34", 34 },
+   { "vs35", 35 },
+   { "vs36", 36 },
+   { "vs37", 37 },
+   { "vs38", 38 },
+   { "vs39", 39 },
+   { "vs4", 4 },
+   { "vs40", 40 },
+   { "vs41", 41 },
+   { "vs42", 42 },
+   { "vs43", 43 },
+   { "vs44", 44 },
+   { "vs45", 45 },
+   { "vs46", 46 },
+   { "vs47", 47 },
+   { "vs48", 48 },
+   { "vs49", 49 },
+   { "vs5", 5 },
+   { "vs50", 50 },
+   { "vs51", 51 },
+   { "vs52", 52 },
+   { "vs53", 53 },
+   { "vs54", 54 },
+   { "vs55", 55 },
+   { "vs56", 56 },
+   { "vs57", 57 },
+   { "vs58", 58 },
+   { "vs59", 59 },
+   { "vs6", 6 },
+   { "vs60", 60 },
+   { "vs61", 61 },
+   { "vs62", 62 },
+   { "vs63", 63 },
+   { "vs7", 7 },
+   { "vs8", 8 },
+   { "vs9", 9 },
+ 
    { "xer", 1 },
  
  };
*************** parse_cpu (const char *arg)
*** 940,947 ****
    else if (strcmp (arg, "power7") == 0)
      {
        ppc_cpu = (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC
! 		 | PPC_OPCODE_64 | PPC_OPCODE_POWER4
! 		 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
  		 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX);
      }
    else if (strcmp (arg, "cell") == 0)
--- 1136,1144 ----
    else if (strcmp (arg, "power7") == 0)
      {
        ppc_cpu = (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC
! 		 | PPC_OPCODE_ISEL | PPC_OPCODE_64
! 		 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5
! 		 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7
  		 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX);
      }
    else if (strcmp (arg, "cell") == 0)
*************** md_assemble (char *str)
*** 2768,2777 ****
  
  #ifdef OBJ_ELF
    /* Do we need/want a APUinfo section? */
!   if (ppc_cpu & (PPC_OPCODE_SPE
!    	       | PPC_OPCODE_ISEL | PPC_OPCODE_EFS
! 	       | PPC_OPCODE_BRLOCK | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK
! 	       | PPC_OPCODE_RFMCI))
      {
        /* These are all version "1".  */
        if (opcode->flags & PPC_OPCODE_SPE)
--- 2965,2971 ----
  
  #ifdef OBJ_ELF
    /* Do we need/want a APUinfo section? */
!   if ((ppc_cpu & PPC_OPCODE_E500MC) != 0)
      {
        /* These are all version "1".  */
        if (opcode->flags & PPC_OPCODE_SPE)
diff -rcp ../binutils-2.19.51.0.2.15/gas/testsuite/gas/ppc/booke.d ./gas/testsuite/gas/ppc/booke.d
*** ../binutils-2.19.51.0.2.15/gas/testsuite/gas/ppc/booke.d	2009-03-02 14:05:01.000000000 +0000
--- ./gas/testsuite/gas/ppc/booke.d	2009-03-05 12:20:26.000000000 +0000
*************** Disassembly of section \.text:
*** 38,40 ****
--- 38,43 ----
    68:	7c 07 42 a6 	mfsprg  r0,7
    6c:	7c 17 43 a6 	mtsprg  7,r0
    70:	7c 17 43 a6 	mtsprg  7,r0
+   74:	7c 05 32 2c 	dcbt    r5,r6
+   78:	7c 05 32 2c 	dcbt    r5,r6
+   7c:	7d 05 32 2c 	dcbt    8,r5,r6
diff -rcp ../binutils-2.19.51.0.2.15/gas/testsuite/gas/ppc/booke.s ./gas/testsuite/gas/ppc/booke.s
*** ../binutils-2.19.51.0.2.15/gas/testsuite/gas/ppc/booke.s	2009-03-02 14:05:01.000000000 +0000
--- ./gas/testsuite/gas/ppc/booke.s	2009-03-05 12:20:26.000000000 +0000
*************** branch_target_2:	
*** 36,38 ****
--- 36,42 ----
  	mfsprg7 0
  	mtsprg 7, 0
  	mtsprg7 0
+ 
+ 	dcbt 5,6
+ 	dcbt 0,5,6
+ 	dcbt 8,5,6
diff -rcp ../binutils-2.19.51.0.2.15/gas/testsuite/gas/ppc/e500mc.d ./gas/testsuite/gas/ppc/e500mc.d
*** ../binutils-2.19.51.0.2.15/gas/testsuite/gas/ppc/e500mc.d	2009-03-02 14:05:01.000000000 +0000
--- ./gas/testsuite/gas/ppc/e500mc.d	2009-03-05 12:20:26.000000000 +0000
***************
*** 6,12 ****
  
  Disassembly of section \.text:
  
! 0+0000000 <start>:
     0:	4c 00 00 4e 	rfdi
     4:	4c 00 00 cc 	rfgi
     8:	4c 1f f9 8c 	dnh     0,1023
--- 6,12 ----
  
  Disassembly of section \.text:
  
! 0+00 <start>:
     0:	4c 00 00 4e 	rfdi
     4:	4c 00 00 cc 	rfgi
     8:	4c 1f f9 8c 	dnh     0,1023
*************** Disassembly of section \.text:
*** 14,51 ****
    10:	7c 09 57 be 	icbiep  r9,r10
    14:	7c 00 69 dc 	msgclr  r13
    18:	7c 00 71 9c 	msgsnd  r14
!   1c:	7c 00 00 7c 	wait
!   20:	7f 9c e3 78 	mdors
!   24:	7c 00 02 1c 	ehpriv
!   28:	7c 18 cb c6 	dsn     r24,r25
!   2c:	7c 22 18 be 	lbepx   r1,r2,r3
!   30:	7c 85 32 3e 	lhepx   r4,r5,r6
!   34:	7c e8 48 3e 	lwepx   r7,r8,r9
!   38:	7d 4b 60 3a 	ldepx   r10,r11,r12
!   3c:	7d ae 7c be 	lfdepx  r13,r14,r15
!   40:	7e 11 91 be 	stbepx  r16,r17,r18
!   44:	7e 74 ab 3e 	sthepx  r19,r20,r21
!   48:	7e d7 c1 3e 	stwepx  r22,r23,r24
!   4c:	7f 3a d9 3a 	stdepx  r25,r26,r27
!   50:	7f 9d f5 be 	stfdepx r28,r29,r30
!   54:	7c 01 14 06 	lbdx    r0,r1,r2
!   58:	7d 8d 74 46 	lhdx    r12,r13,r14
!   5c:	7c 64 2c 86 	lwdx    r3,r4,r5
!   60:	7f 5b e6 46 	lfddx   f26,r27,r28
!   64:	7d f0 8c c6 	lddx    r15,r16,r17
!   68:	7c c7 45 06 	stbdx   r6,r7,r8
!   6c:	7e 53 a5 46 	sthdx   r18,r19,r20
!   70:	7d 2a 5d 86 	stwdx   r9,r10,r11
!   74:	7f be ff 46 	stfddx  f29,r30,r31
!   78:	7e b6 bd c6 	stddx   r21,r22,r23
!   7c:	7c 20 0d ec 	dcbal   r0,r1
!   80:	7c 26 3f ec 	dcbzl   r6,r7
!   84:	7c 1f 00 7e 	dcbstep r31,r0
!   88:	7c 01 10 fe 	dcbfep  r1,r2
!   8c:	7c 64 29 fe 	dcbtstep r3,r4,r5
!   90:	7c c7 42 7e 	dcbtep  r6,r7,r8
!   94:	7c 0b 67 fe 	dcbzep  r11,r12
!   98:	7c 00 06 26 	tlbilx  0,0,r0
!   9c:	7c 20 06 26 	tlbilx  1,0,r0
!   a0:	7c 62 1e 26 	tlbilx  3,r2,r3
!   a4:	7c 64 2e 26 	tlbilx  3,r4,r5
--- 14,56 ----
    10:	7c 09 57 be 	icbiep  r9,r10
    14:	7c 00 69 dc 	msgclr  r13
    18:	7c 00 71 9c 	msgsnd  r14
!   1c:	7c 00 00 7c 	wait    
!   20:	7c 00 00 7c 	wait    
!   24:	7c 20 00 7c 	waitrsv
!   28:	7c 20 00 7c 	waitrsv
!   2c:	7c 40 00 7c 	waitimpl
!   30:	7c 40 00 7c 	waitimpl
!   34:	7f 9c e3 78 	mdors
!   38:	7c 00 02 1c 	ehpriv
!   3c:	7c 18 cb c6 	dsn     r24,r25
!   40:	7c 22 18 be 	lbepx   r1,r2,r3
!   44:	7c 85 32 3e 	lhepx   r4,r5,r6
!   48:	7c e8 48 3e 	lwepx   r7,r8,r9
!   4c:	7d 4b 60 3a 	ldepx   r10,r11,r12
!   50:	7d ae 7c be 	lfdepx  f13,r14,r15
!   54:	7e 11 91 be 	stbepx  r16,r17,r18
!   58:	7e 74 ab 3e 	sthepx  r19,r20,r21
!   5c:	7e d7 c1 3e 	stwepx  r22,r23,r24
!   60:	7f 3a d9 3a 	stdepx  r25,r26,r27
!   64:	7f 9d f5 be 	stfdepx f28,r29,r30
!   68:	7c 01 14 06 	lbdx    r0,r1,r2
!   6c:	7d 8d 74 46 	lhdx    r12,r13,r14
!   70:	7c 64 2c 86 	lwdx    r3,r4,r5
!   74:	7f 5b e6 46 	lfddx   f26,r27,r28
!   78:	7d f0 8c c6 	lddx    r15,r16,r17
!   7c:	7c c7 45 06 	stbdx   r6,r7,r8
!   80:	7e 53 a5 46 	sthdx   r18,r19,r20
!   84:	7d 2a 5d 86 	stwdx   r9,r10,r11
!   88:	7f be ff 46 	stfddx  f29,r30,r31
!   8c:	7e b6 bd c6 	stddx   r21,r22,r23
!   90:	7c 20 0d ec 	dcbal   r0,r1
!   94:	7c 26 3f ec 	dcbzl   r6,r7
!   98:	7c 1f 00 7e 	dcbstep r31,r0
!   9c:	7c 01 10 fe 	dcbfep  r1,r2
!   a0:	7c 64 29 fe 	dcbtstep r3,r4,r5
!   a4:	7c c7 42 7e 	dcbtep  r6,r7,r8
!   a8:	7c 0b 67 fe 	dcbzep  r11,r12
!   ac:	7c 00 06 26 	tlbilx  0,0,r0
!   b0:	7c 20 06 26 	tlbilx  1,0,r0
!   b4:	7c 62 1e 26 	tlbilx  3,r2,r3
!   b8:	7c 64 2e 26 	tlbilx  3,r4,r5
diff -rcp ../binutils-2.19.51.0.2.15/gas/testsuite/gas/ppc/e500mc.s ./gas/testsuite/gas/ppc/e500mc.s
*** ../binutils-2.19.51.0.2.15/gas/testsuite/gas/ppc/e500mc.s	2009-03-02 14:05:01.000000000 +0000
--- ./gas/testsuite/gas/ppc/e500mc.s	2009-03-05 12:20:26.000000000 +0000
*************** start:
*** 9,14 ****
--- 9,19 ----
  	msgclr	13
  	msgsnd	14
  	wait
+ 	wait 0
+ 	waitrsv
+ 	wait 1
+ 	waitimpl
+ 	wait 2
  	mdors
  	ehpriv
  	dsn	24, 25
diff -rcp ../binutils-2.19.51.0.2.15/gas/testsuite/gas/ppc/power4_32.d ./gas/testsuite/gas/ppc/power4_32.d
*** ../binutils-2.19.51.0.2.15/gas/testsuite/gas/ppc/power4_32.d	2009-03-02 14:05:01.000000000 +0000
--- ./gas/testsuite/gas/ppc/power4_32.d	2009-03-05 12:20:26.000000000 +0000
*************** Disassembly of section \.text:
*** 41,43 ****
--- 41,46 ----
    7c:	7c 01 17 ec 	dcbz    r1,r2
    80:	7c 23 27 ec 	dcbzl   r3,r4
    84:	7c 05 37 ec 	dcbz    r5,r6
+   88:	7c 05 32 2c 	dcbt    r5,r6
+   8c:	7c 05 32 2c 	dcbt    r5,r6
+   90:	7d 05 32 2c 	dcbt    r5,r6,8
diff -rcp ../binutils-2.19.51.0.2.15/gas/testsuite/gas/ppc/power4_32.s ./gas/testsuite/gas/ppc/power4_32.s
*** ../binutils-2.19.51.0.2.15/gas/testsuite/gas/ppc/power4_32.s	2009-03-02 14:05:01.000000000 +0000
--- ./gas/testsuite/gas/ppc/power4_32.s	2009-03-05 12:20:26.000000000 +0000
*************** start:
*** 34,36 ****
--- 34,39 ----
  	dcbz    1, 2
  	dcbzl   3, 4
  	dcbz    5, 6
+ 	dcbt    5,6
+ 	dcbt    5,6,0
+ 	dcbt    5,6,8
diff -rcp ../binutils-2.19.51.0.2.15/gas/testsuite/gas/ppc/power6.d ./gas/testsuite/gas/ppc/power6.d
*** ../binutils-2.19.51.0.2.15/gas/testsuite/gas/ppc/power6.d	2009-03-02 14:05:01.000000000 +0000
--- ./gas/testsuite/gas/ppc/power6.d	2009-03-05 12:20:26.000000000 +0000
*************** Disassembly of section \.text:
*** 66,68 ****
--- 66,71 ----
    e0:	ff 00 f1 0d 	mtfsfi. 6,15
    e4:	ff 01 01 0c 	mtfsfi  6,0,1
    e8:	ff 01 f1 0d 	mtfsfi. 6,15,1
+   ec:	7d 6a 02 74 	cbcdtd  r10,r11
+   f0:	7d 6a 02 34 	cdtbcd  r10,r11
+   f4:	7d 4b 60 94 	addg6s  r10,r11,r12
diff -rcp ../binutils-2.19.51.0.2.15/gas/testsuite/gas/ppc/power6.s ./gas/testsuite/gas/ppc/power6.s
*** ../binutils-2.19.51.0.2.15/gas/testsuite/gas/ppc/power6.s	2009-03-02 14:05:01.000000000 +0000
--- ./gas/testsuite/gas/ppc/power6.s	2009-03-05 12:20:26.000000000 +0000
*************** start:
*** 61,63 ****
--- 61,66 ----
  	mtfsfi. 6,15,0
  	mtfsfi  6,0,1
  	mtfsfi. 6,15,1
+ 	cbcdtd  10,11
+ 	cdtbcd  10,11
+ 	addg6s  10,11,12
diff -rcp ../binutils-2.19.51.0.2.15/gas/testsuite/gas/ppc/power7.d ./gas/testsuite/gas/ppc/power7.d
*** ../binutils-2.19.51.0.2.15/gas/testsuite/gas/ppc/power7.d	2009-03-02 14:05:01.000000000 +0000
--- ./gas/testsuite/gas/ppc/power7.d	2009-03-05 12:20:26.000000000 +0000
***************
*** 1,8 ****
! #as: -a32 -mpower7
  #objdump: -dr -Mpower7
  #name: POWER7 tests (includes DFP, Altivec and VSX)
  
! .*: +file format elf32-powerpc.*
  
  Disassembly of section \.text:
  
--- 1,8 ----
! #as: -mpower7
  #objdump: -dr -Mpower7
  #name: POWER7 tests (includes DFP, Altivec and VSX)
  
! .*: +file format elf(32)?(64)?-powerpc.*
  
  Disassembly of section \.text:
  
*************** Disassembly of section \.text:
*** 33,57 ****
    5c:	f1 6c 67 87 	xvmovdp vs43,vs44
    60:	f0 64 2f 80 	xvcpsgndp vs3,vs4,vs5
    64:	f1 6c 6f 87 	xvcpsgndp vs43,vs44,vs45
!   68:	4c 00 03 24 	doze
!   6c:	4c 00 03 64 	nap
!   70:	4c 00 03 a4 	sleep
!   74:	4c 00 03 e4 	rvwinkle
!   78:	7c 83 01 34 	prtyw   r3,r4
!   7c:	7d cd 01 74 	prtyd   r13,r14
!   80:	7d 5c 02 a6 	mfcfar  r10
!   84:	7d 7c 03 a6 	mtcfar  r11
!   88:	7c 83 2b f8 	cmpb    r3,r4,r5
!   8c:	7c c0 3c be 	mffgpr  f6,r7
!   90:	7d 00 4d be 	mftgpr  r8,f9
!   94:	7d 4b 66 2a 	lwzcix  r10,r11,r12
!   98:	7d ae 7e 2e 	lfdpx   f13,r14,r15
!   9c:	ee 11 90 04 	dadd    f16,f17,f18
!   a0:	fe 96 c0 04 	daddq   f20,f22,f24
!   a4:	7c 60 06 6c 	dss     3
!   a8:	7e 00 06 6c 	dssall
!   ac:	7c 25 22 ac 	dst     r5,r4,1
!   b0:	7e 08 3a ac 	dstt    r8,r7,0
!   b4:	7c 65 32 ec 	dstst   r5,r6,3
!   b8:	7e 44 2a ec 	dststt  r4,r5,2
!   bc:	4e 80 00 20 	blr
--- 33,113 ----
    5c:	f1 6c 67 87 	xvmovdp vs43,vs44
    60:	f0 64 2f 80 	xvcpsgndp vs3,vs4,vs5
    64:	f1 6c 6f 87 	xvcpsgndp vs43,vs44,vs45
!   68:	7c 00 00 7c 	wait    
!   6c:	7c 00 00 7c 	wait    
!   70:	7c 20 00 7c 	waitrsv
!   74:	7c 20 00 7c 	waitrsv
!   78:	7c 40 00 7c 	waitimpl
!   7c:	7c 40 00 7c 	waitimpl
!   80:	4c 00 03 24 	doze
!   84:	4c 00 03 64 	nap
!   88:	4c 00 03 a4 	sleep
!   8c:	4c 00 03 e4 	rvwinkle
!   90:	7c 83 01 34 	prtyw   r3,r4
!   94:	7d cd 01 74 	prtyd   r13,r14
!   98:	7d 5c 02 a6 	mfcfar  r10
!   9c:	7d 7c 03 a6 	mtcfar  r11
!   a0:	7c 83 2b f8 	cmpb    r3,r4,r5
!   a4:	7d 4b 66 2a 	lwzcix  r10,r11,r12
!   a8:	ee 11 90 04 	dadd    f16,f17,f18
!   ac:	fe 96 c0 04 	daddq   f20,f22,f24
!   b0:	7c 60 06 6c 	dss     3
!   b4:	7e 00 06 6c 	dssall
!   b8:	7c 25 22 ac 	dst     r5,r4,1
!   bc:	7e 08 3a ac 	dstt    r8,r7,0
!   c0:	7c 65 32 ec 	dstst   r5,r6,3
!   c4:	7e 44 2a ec 	dststt  r4,r5,2
!   c8:	7d 4b 63 56 	divwe   r10,r11,r12
!   cc:	7d 6c 6b 57 	divwe\.  r11,r12,r13
!   d0:	7d 8d 77 56 	divweo  r12,r13,r14
!   d4:	7d ae 7f 57 	divweo\. r13,r14,r15
!   d8:	7d 4b 63 16 	divweu  r10,r11,r12
!   dc:	7d 6c 6b 17 	divweu\. r11,r12,r13
!   e0:	7d 8d 77 16 	divweuo r12,r13,r14
!   e4:	7d ae 7f 17 	divweuo\. r13,r14,r15
!   e8:	7e 27 d9 f8 	bpermd  r7,r17,r27
!   ec:	7e 8a 02 f4 	popcntw r10,r20
!   f0:	7e 8a 03 f4 	popcntd r10,r20
!   f4:	7e 95 b4 28 	ldbrx   r20,r21,r22
!   f8:	7e 95 b5 28 	stdbrx  r20,r21,r22
!   fc:	7d 40 56 ee 	lfiwzx  f10,0,r10
!  100:	7d 49 56 ee 	lfiwzx  f10,r9,r10
!  104:	ec 80 2e 9c 	fcfids  f4,f5
!  108:	ec 80 2e 9d 	fcfids\. f4,f5
!  10c:	ec 80 2f 9c 	fcfidus f4,f5
!  110:	ec 80 2f 9d 	fcfidus\. f4,f5
!  114:	fc 80 29 1c 	fctiwu  f4,f5
!  118:	fc 80 29 1d 	fctiwu\. f4,f5
!  11c:	fc 80 29 1e 	fctiwuz f4,f5
!  120:	fc 80 29 1f 	fctiwuz\. f4,f5
!  124:	fc 80 2f 5c 	fctidu  f4,f5
!  128:	fc 80 2f 5d 	fctidu\. f4,f5
!  12c:	fc 80 2f 5e 	fctiduz f4,f5
!  130:	fc 80 2f 5f 	fctiduz\. f4,f5
!  134:	fc 80 2f 9c 	fcfidu  f4,f5
!  138:	fc 80 2f 9d 	fcfidu\. f4,f5
!  13c:	fc 0a 59 00 	ftdiv   cr0,f10,f11
!  140:	ff 8a 59 00 	ftdiv   cr7,f10,f11
!  144:	fc 00 51 40 	ftsqrt  cr0,f10
!  148:	ff 80 51 40 	ftsqrt  cr7,f10
!  14c:	7e 08 4a 2c 	dcbtt   r8,r9
!  150:	7e 08 49 ec 	dcbtstt r8,r9
!  154:	ed 40 66 44 	dcffix  f10,f12
!  158:	ee 80 b6 45 	dcffix\. f20,f22
!  15c:	7d 4b 60 68 	lbarx   r10,r11,r12
!  160:	7d 4b 60 68 	lbarx   r10,r11,r12
!  164:	7d 4b 60 69 	lbarx   r10,r11,r12,1
!  168:	7e 95 b0 e8 	lharx   r20,r21,r22
!  16c:	7e 95 b0 e8 	lharx   r20,r21,r22
!  170:	7e 95 b0 e9 	lharx   r20,r21,r22,1
!  174:	7d 4b 65 6d 	stbcx\.  r10,r11,r12
!  178:	7d 4b 65 ad 	sthcx\.  r10,r11,r12
!  17c:	fd c0 78 30 	fre     f14,f15
!  180:	fd c0 78 31 	fre\.    f14,f15
!  184:	ed c0 78 30 	fres    f14,f15
!  188:	ed c0 78 31 	fres\.   f14,f15
!  18c:	fd c0 78 34 	frsqrte f14,f15
!  190:	fd c0 78 35 	frsqrte\. f14,f15
!  194:	ed c0 78 34 	frsqrtes f14,f15
!  198:	ed c0 78 35 	frsqrtes\. f14,f15
!  19c:	7c 43 27 1e 	isel    r2,r3,r4,28
diff -rcp ../binutils-2.19.51.0.2.15/gas/testsuite/gas/ppc/power7.s ./gas/testsuite/gas/ppc/power7.s
*** ../binutils-2.19.51.0.2.15/gas/testsuite/gas/ppc/power7.s	2009-03-02 14:05:01.000000000 +0000
--- ./gas/testsuite/gas/ppc/power7.s	2009-03-05 12:20:26.000000000 +0000
***************
*** 1,9 ****
- 	.file	"power7.c"
  	.section	".text"
- 	.align 2
- 	.p2align 4,,15
- 	.globl power7
- 	.type	power7, @function
  power7:
  	lxvd2x    3,4,5
  	lxvd2ux   3,4,5
--- 1,4 ----
*************** power7:
*** 31,36 ****
--- 26,37 ----
  	xvcpsgndp 43,44,44
  	xvcpsgndp 3,4,5
  	xvcpsgndp 43,44,45
+ 	wait
+ 	wait 0
+ 	waitrsv
+ 	wait 1
+ 	waitimpl
+ 	wait 2
  	doze
  	nap
  	sleep
*************** power7:
*** 40,49 ****
  	mfcfar    10
  	mtcfar    11
  	cmpb      3,4,5
- 	mffgpr    6,7
- 	mftgpr    8,9
  	lwzcix    10,11,12
- 	lfdpx     13,14,15
  	dadd      16,17,18
  	daddq     20,22,24
  	dss       3
--- 41,47 ----
*************** power7:
*** 52,58 ****
  	dstt      8,7,0
  	dstst     5,6,3
  	dststt    4,5,2
! 	blr
! 	.size	power7,.-power7
! 	.ident	"GCC: (GNU) 4.1.2 20070115 (prerelease) (SUSE Linux)"
! 	.section	.note.GNU-stack,"",@progbits
--- 50,106 ----
  	dstt      8,7,0
  	dstst     5,6,3
  	dststt    4,5,2
! 	divwe	  10,11,12
! 	divwe.	  11,12,13
! 	divweo	  12,13,14
! 	divweo.	  13,14,15
! 	divweu	  10,11,12
! 	divweu.	  11,12,13
! 	divweuo	  12,13,14
! 	divweuo.  13,14,15
! 	bpermd    7,17,27
! 	popcntw   10,20
! 	popcntd   10,20
! 	ldbrx     20,21,22
! 	stdbrx    20,21,22
! 	lfiwzx	  10,0,10
! 	lfiwzx	  10,9,10
! 	fcfids    4,5
! 	fcfids.   4,5
! 	fcfidus   4,5
! 	fcfidus.  4,5
! 	fctiwu    4,5
! 	fctiwu.   4,5
! 	fctiwuz   4,5
! 	fctiwuz.  4,5
! 	fctidu    4,5
! 	fctidu.   4,5
! 	fctiduz   4,5
! 	fctiduz.  4,5
! 	fcfidu    4,5
! 	fcfidu.   4,5
! 	ftdiv     0,10,11
! 	ftdiv     7,10,11
! 	ftsqrt    0,10
! 	ftsqrt    7,10
! 	dcbtt     8,9
! 	dcbtstt   8,9
! 	dcffix    10,12
! 	dcffix.   20,22
! 	lbarx     10,11,12
! 	lbarx     10,11,12,0
! 	lbarx     10,11,12,1
! 	lharx     20,21,22
! 	lharx     20,21,22,0
! 	lharx     20,21,22,1
! 	stbcx.    10,11,12
! 	sthcx.    10,11,12
! 	fre       14,15
! 	fre.      14,15
! 	fres      14,15
! 	fres.     14,15
! 	frsqrte   14,15
! 	frsqrte.  14,15
! 	frsqrtes  14,15
! 	frsqrtes. 14,15
! 	isel	  2,3,4,28
diff -rcp ../binutils-2.19.51.0.2.15/gas/testsuite/gas/ppc/ppc.exp ./gas/testsuite/gas/ppc/ppc.exp
*** ../binutils-2.19.51.0.2.15/gas/testsuite/gas/ppc/ppc.exp	2009-03-02 14:05:01.000000000 +0000
--- ./gas/testsuite/gas/ppc/ppc.exp	2009-03-05 12:20:26.000000000 +0000
*************** if { [istarget powerpc*-*-*] } then {
*** 47,51 ****
--- 47,52 ----
  	run_dump_test "power4_32"
  	run_dump_test "power6"
  	run_dump_test "power7"
+ 	run_dump_test "vsx"
      }
  }
Only in ./gas/testsuite/gas/ppc: vsx.d
Only in ./gas/testsuite/gas/ppc: vsx.s
diff -rcp ../binutils-2.19.51.0.2.15/include/opcode/ppc.h ./include/opcode/ppc.h
*** ../binutils-2.19.51.0.2.15/include/opcode/ppc.h	2009-03-02 14:04:52.000000000 +0000
--- ./include/opcode/ppc.h	2009-03-05 12:20:26.000000000 +0000
*************** extern const int powerpc_num_opcodes;
*** 114,119 ****
--- 114,122 ----
  /* Opcode is only supported by Power4 architecture.  */
  #define PPC_OPCODE_POWER4	    0x4000
  
+ /* Opcode is only supported by Power7 architecture.  */
+ #define PPC_OPCODE_POWER7	    0x8000
+ 
  /* Opcode is only supported by POWERPC Classic architecture.  */
  #define PPC_OPCODE_CLASSIC	   0x10000
  
diff -rcp ../binutils-2.19.51.0.2.15/ld/emultempl/beos.em ./ld/emultempl/beos.em
*** ../binutils-2.19.51.0.2.15/ld/emultempl/beos.em	2009-03-02 14:04:53.000000000 +0000
--- ./ld/emultempl/beos.em	2009-03-05 12:20:26.000000000 +0000
*************** fi
*** 8,14 ****
  fragment <<EOF
  /* This file is part of GLD, the Gnu Linker.
     Copyright 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004,
!    2005, 2006, 2007, 2008 Free Software Foundation, Inc.
  
     This file is part of the GNU Binutils.
  
--- 8,14 ----
  fragment <<EOF
  /* This file is part of GLD, the Gnu Linker.
     Copyright 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004,
!    2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
  
     This file is part of the GNU Binutils.
  
*************** gld_${EMULATION_NAME}_set_symbols (void)
*** 330,336 ****
    /* Run through and invent symbols for all the
       names and insert the defaults. */
    int j;
-   lang_statement_list_type *save;
  
    if (!init[IMAGEBASEOFF].inited)
      {
--- 330,335 ----
*************** gld_${EMULATION_NAME}_set_symbols (void)
*** 347,355 ****
      return;
  
    /* Glue the assignments into the abs section */
!   save = stat_ptr;
! 
!   stat_ptr = &(abs_output_section->children);
  
    for (j = 0; init[j].ptr; j++)
      {
--- 346,352 ----
      return;
  
    /* Glue the assignments into the abs section */
!   push_stat_ptr (&abs_output_section->children);
  
    for (j = 0; init[j].ptr; j++)
      {
*************** gld_${EMULATION_NAME}_set_symbols (void)
*** 367,373 ****
        else	abort();
      }
    /* Restore the pointer. */
!   stat_ptr = save;
  
    if (pe.FileAlignment >
        pe.SectionAlignment)
--- 364,370 ----
        else	abort();
      }
    /* Restore the pointer. */
!   pop_stat_ptr ();
  
    if (pe.FileAlignment >
        pe.SectionAlignment)
*************** sort_sections (lang_statement_union_type
*** 609,616 ****
  static void
  gld_${EMULATION_NAME}_before_allocation (void)
  {
-   extern lang_statement_list_type *stat_ptr;
- 
  #ifdef TARGET_IS_ppcpe
    /* Here we rummage through the found bfds to collect toc information */
    {
--- 606,611 ----
diff -rcp ../binutils-2.19.51.0.2.15/ld/emultempl/pe.em ./ld/emultempl/pe.em
*** ../binutils-2.19.51.0.2.15/ld/emultempl/pe.em	2009-03-02 14:04:53.000000000 +0000
--- ./ld/emultempl/pe.em	2009-03-05 12:20:26.000000000 +0000
*************** rm -f e${EMULATION_NAME}.c
*** 10,16 ****
  (echo;echo;echo;echo;echo)>e${EMULATION_NAME}.c # there, now line numbers match ;-)
  fragment <<EOF
  /* Copyright 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004,
!    2005, 2006, 2007, 2008 Free Software Foundation, Inc.
  
     This file is part of the GNU Binutils.
  
--- 10,16 ----
  (echo;echo;echo;echo;echo)>e${EMULATION_NAME}.c # there, now line numbers match ;-)
  fragment <<EOF
  /* Copyright 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004,
!    2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
  
     This file is part of the GNU Binutils.
  
*************** gld_${EMULATION_NAME}_set_symbols (void)
*** 725,731 ****
    /* Run through and invent symbols for all the
       names and insert the defaults.  */
    int j;
-   lang_statement_list_type *save;
  
    if (!init[IMAGEBASEOFF].inited)
      {
--- 725,730 ----
*************** gld_${EMULATION_NAME}_set_symbols (void)
*** 748,756 ****
      return;
  
    /* Glue the assignments into the abs section.  */
!   save = stat_ptr;
! 
!   stat_ptr = &(abs_output_section->children);
  
    for (j = 0; init[j].ptr; j++)
      {
--- 747,753 ----
      return;
  
    /* Glue the assignments into the abs section.  */
!   push_stat_ptr (&abs_output_section->children);
  
    for (j = 0; init[j].ptr; j++)
      {
*************** gld_${EMULATION_NAME}_set_symbols (void)
*** 772,778 ****
  	image_base_statement = rv;
      }
    /* Restore the pointer.  */
!   stat_ptr = save;
  
    if (pe.FileAlignment >
        pe.SectionAlignment)
--- 769,775 ----
  	image_base_statement = rv;
      }
    /* Restore the pointer.  */
!   pop_stat_ptr ();
  
    if (pe.FileAlignment >
        pe.SectionAlignment)
diff -rcp ../binutils-2.19.51.0.2.15/ld/emultempl/pep.em ./ld/emultempl/pep.em
*** ../binutils-2.19.51.0.2.15/ld/emultempl/pep.em	2009-03-02 14:04:53.000000000 +0000
--- ./ld/emultempl/pep.em	2009-03-05 12:20:26.000000000 +0000
*************** fi
*** 9,15 ****
  rm -f e${EMULATION_NAME}.c
  (echo;echo;echo;echo;echo)>e${EMULATION_NAME}.c # there, now line numbers match ;-)
  fragment <<EOF
! /* Copyright 2006, 2007, 2008 Free Software Foundation, Inc.
     Written by Kai Tietz, OneVision Software GmbH&CoKg.
  
     This file is part of the GNU Binutils.
--- 9,15 ----
  rm -f e${EMULATION_NAME}.c
  (echo;echo;echo;echo;echo)>e${EMULATION_NAME}.c # there, now line numbers match ;-)
  fragment <<EOF
! /* Copyright 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
     Written by Kai Tietz, OneVision Software GmbH&CoKg.
  
     This file is part of the GNU Binutils.
*************** gld_${EMULATION_NAME}_set_symbols (void)
*** 681,687 ****
    /* Run through and invent symbols for all the
       names and insert the defaults.  */
    int j;
-   lang_statement_list_type *save;
  
    if (!init[IMAGEBASEOFF].inited)
      {
--- 681,686 ----
*************** gld_${EMULATION_NAME}_set_symbols (void)
*** 704,712 ****
      return;
  
    /* Glue the assignments into the abs section.  */
!   save = stat_ptr;
! 
!   stat_ptr = &(abs_output_section->children);
  
    for (j = 0; init[j].ptr; j++)
      {
--- 703,709 ----
      return;
  
    /* Glue the assignments into the abs section.  */
!   push_stat_ptr (&abs_output_section->children);
  
    for (j = 0; init[j].ptr; j++)
      {
*************** gld_${EMULATION_NAME}_set_symbols (void)
*** 728,734 ****
  	image_base_statement = rv;
      }
    /* Restore the pointer.  */
!   stat_ptr = save;
  
    if (pep.FileAlignment > pep.SectionAlignment)
      {
--- 725,731 ----
  	image_base_statement = rv;
      }
    /* Restore the pointer.  */
!   pop_stat_ptr ();
  
    if (pep.FileAlignment > pep.SectionAlignment)
      {
diff -rcp ../binutils-2.19.51.0.2.15/ld/emultempl/xtensaelf.em ./ld/emultempl/xtensaelf.em
*** ../binutils-2.19.51.0.2.15/ld/emultempl/xtensaelf.em	2009-03-02 14:04:53.000000000 +0000
--- ./ld/emultempl/xtensaelf.em	2009-03-05 12:20:26.000000000 +0000
***************
*** 1,5 ****
  # This shell script emits a C file. -*- C -*-
! #   Copyright 2003, 2004, 2005, 2006, 2007, 2008
  #   Free Software Foundation, Inc.
  #
  # This file is part of the GNU Binutils.
--- 1,5 ----
  # This shell script emits a C file. -*- C -*-
! #   Copyright 2003, 2004, 2005, 2006, 2007, 2008, 2009
  #   Free Software Foundation, Inc.
  #
  # This file is part of the GNU Binutils.
*************** ld_xtensa_insert_page_offsets (bfd_vma d
*** 1951,1970 ****
  		lang_assignment_statement_type *assign_stmt;
  		lang_statement_union_type *assign_union;
  		lang_statement_list_type tmplist;
- 		lang_statement_list_type *old_stat_ptr = stat_ptr;
  
  		/* There is hidden state in "lang_add_assignment".  It
  		   appends the new assignment statement to the stat_ptr
  		   list.  Thus, we swap it before and after the call.  */
  
! 		tmplist.head = NULL;
! 		tmplist.tail = &tmplist.head;
! 
! 		stat_ptr = &tmplist;
  		/* Warning: side effect; statement appended to stat_ptr.  */
  		assign_stmt = lang_add_assignment (assign_op);
  		assign_union = (lang_statement_union_type *) assign_stmt;
! 		stat_ptr = old_stat_ptr;
  
  		assign_union->header.next = l;
  		*(*stack_p)->iterloc.loc = assign_union;
--- 1951,1967 ----
  		lang_assignment_statement_type *assign_stmt;
  		lang_statement_union_type *assign_union;
  		lang_statement_list_type tmplist;
  
  		/* There is hidden state in "lang_add_assignment".  It
  		   appends the new assignment statement to the stat_ptr
  		   list.  Thus, we swap it before and after the call.  */
  
! 		lang_list_init (&tmplist);
! 		push_stat_ptr (&tmplist);
  		/* Warning: side effect; statement appended to stat_ptr.  */
  		assign_stmt = lang_add_assignment (assign_op);
  		assign_union = (lang_statement_union_type *) assign_stmt;
! 		pop_stat_ptr ();
  
  		assign_union->header.next = l;
  		*(*stack_p)->iterloc.loc = assign_union;
diff -rcp ../binutils-2.19.51.0.2.15/ld/ldctor.c ./ld/ldctor.c
*** ../binutils-2.19.51.0.2.15/ld/ldctor.c	2009-03-02 14:04:56.000000000 +0000
--- ./ld/ldctor.c	2009-03-05 12:20:26.000000000 +0000
***************
*** 1,6 ****
  /* ldctor.c -- constructor support routines
     Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
!    2002, 2003, 2004, 2006, 2007, 2008 Free Software Foundation, Inc.
     By Steve Chamberlain <sac@cygnus.com>
  
     This file is part of the GNU Binutils.
--- 1,7 ----
  /* ldctor.c -- constructor support routines
     Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
!    2002, 2003, 2004, 2006, 2007, 2008, 2009
!    Free Software Foundation, Inc.
     By Steve Chamberlain <sac@cygnus.com>
  
     This file is part of the GNU Binutils.
*************** void
*** 198,204 ****
  ldctor_build_sets (void)
  {
    static bfd_boolean called;
-   lang_statement_list_type *old;
    bfd_boolean header_printed;
    struct set_info *p;
  
--- 199,204 ----
*************** ldctor_build_sets (void)
*** 244,253 ****
  	}
      }
  
!   old = stat_ptr;
!   stat_ptr = &constructor_list;
! 
!   lang_list_init (stat_ptr);
  
    header_printed = FALSE;
    for (p = sets; p != NULL; p = p->next)
--- 244,251 ----
  	}
      }
  
!   lang_list_init (&constructor_list);
!   push_stat_ptr (&constructor_list);
  
    header_printed = FALSE;
    for (p = sets; p != NULL; p = p->next)
*************** ldctor_build_sets (void)
*** 372,376 ****
        lang_add_data (size, exp_intop (0));
      }
  
!   stat_ptr = old;
  }
--- 370,374 ----
        lang_add_data (size, exp_intop (0));
      }
  
!   pop_stat_ptr ();
  }
diff -rcp ../binutils-2.19.51.0.2.15/ld/ldlang.c ./ld/ldlang.c
*** ../binutils-2.19.51.0.2.15/ld/ldlang.c	2009-03-02 14:04:56.000000000 +0000
--- ./ld/ldlang.c	2009-03-05 12:20:26.000000000 +0000
***************
*** 1,6 ****
  /* Linker command language support.
     Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
!    2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
     Free Software Foundation, Inc.
  
     This file is part of the GNU Binutils.
--- 1,6 ----
  /* Linker command language support.
     Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
!    2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
     Free Software Foundation, Inc.
  
     This file is part of the GNU Binutils.
*************** static const char *current_target;
*** 64,69 ****
--- 64,71 ----
  static const char *output_target;
  static lang_statement_list_type statement_list;
  static struct bfd_hash_table lang_definedness_table;
+ static lang_statement_list_type *stat_save[10];
+ static lang_statement_list_type **stat_save_ptr = &stat_save[0];
  
  /* Forward declarations.  */
  static void exp_init_os (etree_type *);
*************** lang_list_init (lang_statement_list_type
*** 925,930 ****
--- 927,949 ----
    list->tail = &list->head;
  }
  
+ void
+ push_stat_ptr (lang_statement_list_type *new_ptr)
+ {
+   if (stat_save_ptr >= stat_save + sizeof (stat_save) / sizeof (stat_save[0]))
+     abort ();
+   *stat_save_ptr++ = stat_ptr;
+   stat_ptr = new_ptr;
+ }
+ 
+ void
+ pop_stat_ptr (void)
+ {
+   if (stat_save_ptr <= stat_save)
+     abort ();
+   stat_ptr = *--stat_save_ptr;
+ }
+ 
  /* Build a new statement node for the parse tree.  */
  
  static lang_statement_union_type *
*************** lang_insert_orphan (asection *s,
*** 1586,1608 ****
  		    etree_type *address,
  		    lang_statement_list_type *add_child)
  {
-   lang_statement_list_type *old;
    lang_statement_list_type add;
    const char *ps;
    lang_output_section_statement_type *os;
    lang_output_section_statement_type **os_tail;
  
-   /* Start building a list of statements for this section.
-      First save the current statement pointer.  */
-   old = stat_ptr;
- 
    /* If we have found an appropriate place for the output section
       statements for this orphan, add them to our own private list,
       inserting them later into the global statement list.  */
    if (after != NULL)
      {
!       stat_ptr = &add;
!       lang_list_init (stat_ptr);
      }
  
    ps = NULL;
--- 1605,1622 ----
  		    etree_type *address,
  		    lang_statement_list_type *add_child)
  {
    lang_statement_list_type add;
    const char *ps;
    lang_output_section_statement_type *os;
    lang_output_section_statement_type **os_tail;
  
    /* If we have found an appropriate place for the output section
       statements for this orphan, add them to our own private list,
       inserting them later into the global statement list.  */
    if (after != NULL)
      {
!       lang_list_init (&add);
!       push_stat_ptr (&add);
      }
  
    ps = NULL;
*************** lang_insert_orphan (asection *s,
*** 1648,1658 ****
      {
        char *symname;
  
-       /* lang_leave_ouput_section_statement resets stat_ptr.
- 	 Put stat_ptr back where we want it.  */
-       if (after != NULL)
- 	stat_ptr = &add;
- 
        symname = (char *) xmalloc (ps - secname + sizeof "__stop_" + 1);
        symname[0] = bfd_get_symbol_leading_char (link_info.output_bfd);
        sprintf (symname + (symname[0] != 0), "__stop_%s", secname);
--- 1662,1667 ----
*************** lang_insert_orphan (asection *s,
*** 1663,1669 ****
  
    /* Restore the global list pointer.  */
    if (after != NULL)
!     stat_ptr = old;
  
    if (after != NULL && os->bfd_section != NULL)
      {
--- 1672,1678 ----
  
    /* Restore the global list pointer.  */
    if (after != NULL)
!     pop_stat_ptr ();
  
    if (after != NULL && os->bfd_section != NULL)
      {
*************** lang_insert_orphan (asection *s,
*** 1749,1756 ****
  
  	  /* Fix the global list pointer if we happened to tack our
  	     new list at the tail.  */
! 	  if (*old->tail == add.head)
! 	    old->tail = add.tail;
  
  	  /* Save the end of this list.  */
  	  place->stmt = add.tail;
--- 1758,1765 ----
  
  	  /* Fix the global list pointer if we happened to tack our
  	     new list at the tail.  */
! 	  if (*stat_ptr->tail == add.head)
! 	    stat_ptr->tail = add.tail;
  
  	  /* Save the end of this list.  */
  	  place->stmt = add.tail;
*************** load_symbols (lang_input_statement_type 
*** 2481,2488 ****
        && ! bfd_check_format_matches (entry->the_bfd, bfd_object, &matching))
      {
        bfd_error_type err;
-       lang_statement_list_type *hold;
-       bfd_boolean bad_load = TRUE;
        bfd_boolean save_ldlang_sysrooted_script;
        bfd_boolean save_as_needed, save_add_needed;
  
--- 2490,2495 ----
*************** load_symbols (lang_input_statement_type 
*** 2505,2512 ****
        else if (err != bfd_error_file_not_recognized
  	       || place == NULL)
  	einfo (_("%F%B: file not recognized: %E\n"), entry->the_bfd);
-       else
- 	bad_load = FALSE;
  
        bfd_close (entry->the_bfd);
        entry->the_bfd = NULL;
--- 2512,2517 ----
*************** load_symbols (lang_input_statement_type 
*** 2514,2521 ****
        /* Try to interpret the file as a linker script.  */
        ldfile_open_command_file (entry->filename);
  
!       hold = stat_ptr;
!       stat_ptr = place;
        save_ldlang_sysrooted_script = ldlang_sysrooted_script;
        ldlang_sysrooted_script = entry->sysrooted;
        save_as_needed = as_needed;
--- 2519,2525 ----
        /* Try to interpret the file as a linker script.  */
        ldfile_open_command_file (entry->filename);
  
!       push_stat_ptr (place);
        save_ldlang_sysrooted_script = ldlang_sysrooted_script;
        ldlang_sysrooted_script = entry->sysrooted;
        save_as_needed = as_needed;
*************** load_symbols (lang_input_statement_type 
*** 2534,2542 ****
        ldlang_sysrooted_script = save_ldlang_sysrooted_script;
        as_needed = save_as_needed;
        add_needed = save_add_needed;
!       stat_ptr = hold;
  
!       return ! bad_load;
      }
  
    if (ldemul_recognized_file (entry))
--- 2538,2546 ----
        ldlang_sysrooted_script = save_ldlang_sysrooted_script;
        as_needed = save_as_needed;
        add_needed = save_add_needed;
!       pop_stat_ptr ();
  
!       return TRUE;
      }
  
    if (ldemul_recognized_file (entry))
*************** open_input_bfds (lang_statement_union_ty
*** 3008,3013 ****
--- 3012,3018 ----
  	case lang_input_statement_enum:
  	  if (s->input_statement.real)
  	    {
+ 	      lang_statement_union_type **os_tail;
  	      lang_statement_list_type add;
  
  	      s->input_statement.target = current_target;
*************** open_input_bfds (lang_statement_union_ty
*** 3023,3028 ****
--- 3028,3034 ----
  				       bfd_archive))
  		s->input_statement.loaded = FALSE;
  
+ 	      os_tail = lang_output_section_statement.tail;
  	      lang_list_init (&add);
  
  	      if (! load_symbols (&s->input_statement, &add))
*************** open_input_bfds (lang_statement_union_ty
*** 3030,3037 ****
  
  	      if (add.head != NULL)
  		{
! 		  *add.tail = s->header.next;
! 		  s->header.next = add.head;
  		}
  	    }
  	  break;
--- 3036,3060 ----
  
  	      if (add.head != NULL)
  		{
! 		  /* If this was a script with output sections then
! 		     tack any added statements on to the end of the
! 		     list.  This avoids having to reorder the output
! 		     section statement list.  Very likely the user
! 		     forgot -T, and whatever we do here will not meet
! 		     naive user expectations.  */
! 		  if (os_tail != lang_output_section_statement.tail)
! 		    {
! 		      einfo (_("%P: warning: %s contains output sections;"
! 			       " did you forget -T?\n"),
! 			     s->input_statement.filename);
! 		      *stat_ptr->tail = add.head;
! 		      stat_ptr->tail = add.tail;
! 		    }
! 		  else
! 		    {
! 		      *add.tail = s->header.next;
! 		      s->header.next = add.head;
! 		    }
  		}
  	    }
  	  break;
*************** lang_enter_output_section_statement (con
*** 5860,5866 ****
    os->block_value = 1;
  
    /* Make next things chain into subchain of this.  */
!   stat_ptr = &os->children;
  
    os->subsection_alignment =
      topower (exp_get_value_int (subalign, -1, "subsection alignment"));
--- 5883,5889 ----
    os->block_value = 1;
  
    /* Make next things chain into subchain of this.  */
!   push_stat_ptr (&os->children);
  
    os->subsection_alignment =
      topower (exp_get_value_int (subalign, -1, "subsection alignment"));
*************** lang_leave_output_section_statement (fil
*** 6469,6475 ****
  		    current_section->addr_tree != NULL);
    current_section->fill = fill;
    current_section->phdrs = phdrs;
!   stat_ptr = &statement_list;
  }
  
  /* Create an absolute symbol with the given name with the value of the
--- 6492,6498 ----
  		    current_section->addr_tree != NULL);
    current_section->fill = fill;
    current_section->phdrs = phdrs;
!   pop_stat_ptr ();
  }
  
  /* Create an absolute symbol with the given name with the value of the
*************** lang_enter_group (void)
*** 6586,6592 ****
  
    g = new_stat (lang_group_statement, stat_ptr);
    lang_list_init (&g->children);
!   stat_ptr = &g->children;
  }
  
  /* Leave a group.  This just resets stat_ptr to start writing to the
--- 6609,6615 ----
  
    g = new_stat (lang_group_statement, stat_ptr);
    lang_list_init (&g->children);
!   push_stat_ptr (&g->children);
  }
  
  /* Leave a group.  This just resets stat_ptr to start writing to the
*************** lang_enter_group (void)
*** 6597,6603 ****
  void
  lang_leave_group (void)
  {
!   stat_ptr = &statement_list;
  }
  
  /* Add a new program header.  This is called for each entry in a PHDRS
--- 6620,6626 ----
  void
  lang_leave_group (void)
  {
!   pop_stat_ptr ();
  }
  
  /* Add a new program header.  This is called for each entry in a PHDRS
diff -rcp ../binutils-2.19.51.0.2.15/ld/ldlang.h ./ld/ldlang.h
*** ../binutils-2.19.51.0.2.15/ld/ldlang.h	2009-03-02 14:04:53.000000000 +0000
--- ./ld/ldlang.h	2009-03-05 12:20:26.000000000 +0000
***************
*** 1,6 ****
  /* ldlang.h - linker command language support
     Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
!    2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
     Free Software Foundation, Inc.
  
     This file is part of the GNU Binutils.
--- 1,6 ----
  /* ldlang.h - linker command language support
     Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
!    2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
     Free Software Foundation, Inc.
  
     This file is part of the GNU Binutils.
*************** extern void lang_add_output_format
*** 550,555 ****
--- 550,559 ----
    (const char *, const char *, const char *, int);
  extern void lang_list_init
    (lang_statement_list_type *);
+ extern void push_stat_ptr
+   (lang_statement_list_type *);
+ extern void pop_stat_ptr
+   (void);
  extern void lang_add_data
    (int type, union etree_union *);
  extern void lang_add_reloc
diff -rcp ../binutils-2.19.51.0.2.15/opcodes/ppc-dis.c ./opcodes/ppc-dis.c
*** ../binutils-2.19.51.0.2.15/opcodes/ppc-dis.c	2009-03-02 14:04:59.000000000 +0000
--- ./opcodes/ppc-dis.c	2009-03-05 12:20:26.000000000 +0000
*************** powerpc_init_dialect (struct disassemble
*** 112,119 ****
  
    if (info->disassembler_options
        && strstr (info->disassembler_options, "power7") != NULL)
!     dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
! 	       | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX;
  
    if (info->disassembler_options
        && strstr (info->disassembler_options, "vsx") != NULL)
--- 112,120 ----
  
    if (info->disassembler_options
        && strstr (info->disassembler_options, "power7") != NULL)
!     dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5
! 	       | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7
! 	       | PPC_OPCODE_ISEL | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX;
  
    if (info->disassembler_options
        && strstr (info->disassembler_options, "vsx") != NULL)
diff -rcp ../binutils-2.19.51.0.2.15/opcodes/ppc-opc.c ./opcodes/ppc-opc.c
*** ../binutils-2.19.51.0.2.15/opcodes/ppc-opc.c	2009-03-02 14:05:00.000000000 +0000
--- ./opcodes/ppc-opc.c	2009-03-05 12:20:26.000000000 +0000
***************
*** 1,6 ****
  /* ppc-opc.c -- PowerPC opcode list
     Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004,
!    2005, 2006, 2007, 2008 Free Software Foundation, Inc.
     Written by Ian Lance Taylor, Cygnus Support
  
     This file is part of the GNU opcodes library.
--- 1,6 ----
  /* ppc-opc.c -- PowerPC opcode list
     Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004,
!    2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
     Written by Ian Lance Taylor, Cygnus Support
  
     This file is part of the GNU opcodes library.
*************** static unsigned long insert_xb6 (unsigne
*** 81,86 ****
--- 81,90 ----
  static long extract_xb6 (unsigned long, ppc_cpu_t, int *);
  static unsigned long insert_xb6s (unsigned long, long, ppc_cpu_t, const char **);
  static long extract_xb6s (unsigned long, ppc_cpu_t, int *);
+ static unsigned long insert_xc6 (unsigned long, long, ppc_cpu_t, const char **);
+ static long extract_xc6 (unsigned long, ppc_cpu_t, int *);
+ static unsigned long insert_dm (unsigned long, long, ppc_cpu_t, const char **);
+ static long extract_dm (unsigned long, ppc_cpu_t, int *);
  
  /* The operands table.
  
*************** const struct powerpc_operand powerpc_ope
*** 310,317 ****
  #define LIA LI + 1
    { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
  
!   /* The LS field in an X (sync) form instruction.  */
  #define LS LIA + 1
    { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
  
    /* The ME field in an M form instruction.  */
--- 314,322 ----
  #define LIA LI + 1
    { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
  
!   /* The LS or WC field in an X (sync or wait) form instruction.  */
  #define LS LIA + 1
+ #define WC LS
    { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
  
    /* The ME field in an M form instruction.  */
*************** const struct powerpc_operand powerpc_ope
*** 607,613 ****
  #define XA6 XT6 + 1
    { 0x3f, -1, insert_xa6, extract_xa6, PPC_OPERAND_VSR },
  
!   /* The XB field in an XX3 form instruction.  This is split.  */
  #define XB6 XA6 + 1
    { 0x3f, -1, insert_xb6, extract_xb6, PPC_OPERAND_VSR },
  
--- 612,618 ----
  #define XA6 XT6 + 1
    { 0x3f, -1, insert_xa6, extract_xa6, PPC_OPERAND_VSR },
  
!   /* The XB field in an XX2 or XX3 form instruction.  This is split.  */
  #define XB6 XA6 + 1
    { 0x3f, -1, insert_xb6, extract_xb6, PPC_OPERAND_VSR },
  
*************** const struct powerpc_operand powerpc_ope
*** 617,625 ****
  #define XB6S XB6 + 1
    { 0x3f, -1, insert_xb6s, extract_xb6s, PPC_OPERAND_FAKE },
  
!   /* The DM field in an XX3 form instruction.  */
! #define DM XB6S + 1
    { 0x3, 8, NULL, NULL, 0 },
  };
  
  const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
--- 622,643 ----
  #define XB6S XB6 + 1
    { 0x3f, -1, insert_xb6s, extract_xb6s, PPC_OPERAND_FAKE },
  
!   /* The XC field in an XX4 form instruction.  This is split.  */
! #define XC6 XB6S + 1
!   { 0x3f, -1, insert_xc6, extract_xc6, PPC_OPERAND_VSR },
! 
!   /* The DM or SHW field in an XX3 form instruction.  */
! #define DM XC6 + 1
! #define SHW DM
    { 0x3, 8, NULL, NULL, 0 },
+ 
+   /* The DM field in an extended mnemonic XX3 form instruction.  */
+ #define DMEX DM + 1
+   { 0x3, 8, insert_dm, extract_dm, 0 },
+ 
+   /* The UIM field in an XX2 form instruction.  */
+ #define UIM DMEX + 1
+   { 0x3, 16, NULL, NULL, 0 },
  };
  
  const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
*************** extract_xb6s (unsigned long insn,
*** 1395,1400 ****
--- 1413,1461 ----
      *invalid = 1;
    return 0;
  }
+ 
+ /* The XC field in an XX4 form instruction.  This is split.  */
+ 
+ static unsigned long
+ insert_xc6 (unsigned long insn,
+ 	    long value,
+ 	    ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ 	    const char **errmsg ATTRIBUTE_UNUSED)
+ {
+   return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 2);
+ }
+ 
+ static long
+ extract_xc6 (unsigned long insn,
+ 	     ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ 	     int *invalid ATTRIBUTE_UNUSED)
+ {
+   return ((insn << 2) & 0x20) | ((insn >> 6) & 0x1f);
+ }
+ 
+ static unsigned long
+ insert_dm (unsigned long insn,
+ 	   long value,
+ 	   ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ 	   const char **errmsg)
+ {
+   if (value != 0 && value != 1)
+     *errmsg = _("invalid constant");
+   return insn | (((value) ? 3 : 0) << 8);
+ }
+ 
+ static long
+ extract_dm (unsigned long insn,
+ 	    ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ 	    int *invalid)
+ {
+   long value;
+ 
+   value = (insn >> 8) & 3;
+   if (value != 0 && value != 3)
+     *invalid = 1;
+   return (value) ? 1 : 0;
+ }
  
  /* Macros used to form opcodes.  */
  
*************** extract_xb6s (unsigned long insn,
*** 1536,1546 ****
  /* An X form instruction.  */
  #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
  
  /* An XX3 form instruction.  */
  #define XX3(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0xff) << 3))
  
! #define XX3DM(op, xop, dm) (XX3 (op, ((unsigned long)(xop) & 0x1f)) \
!   | ((((unsigned long)(dm)) & 0x3) << 8))
  
  /* A Z form instruction.  */
  #define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
--- 1597,1613 ----
  /* An X form instruction.  */
  #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
  
+ /* An XX2 form instruction.  */
+ #define XX2(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2))
+ 
  /* An XX3 form instruction.  */
  #define XX3(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0xff) << 3))
  
! /* An XX3 form instruction with the RC bit specified.  */
! #define XX3RC(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | ((((unsigned long)(xop)) & 0x7f) << 3))
! 
! /* An XX4 form instruction.  */
! #define XX4(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3) << 4))
  
  /* A Z form instruction.  */
  #define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
*************** extract_xb6s (unsigned long insn,
*** 1557,1567 ****
  /* The mask for an XX1 form instruction.  */
  #define XX1_MASK X (0x3f, 0x3ff)
  
  /* The mask for an XX3 form instruction.  */
  #define XX3_MASK XX3 (0x3f, 0xff)
  
! /* The mask for an XX3 form instruction with the DM bits specified.  */
  #define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10))
  
  /* The mask for a Z form instruction.  */
  #define Z_MASK ZRC (0x3f, 0x1ff, 1)
--- 1624,1653 ----
  /* The mask for an XX1 form instruction.  */
  #define XX1_MASK X (0x3f, 0x3ff)
  
+ /* The mask for an XX2 form instruction.  */
+ #define XX2_MASK (XX2 (0x3f, 0x1ff) | (0x1f << 16))
+ 
+ /* The mask for an XX2 form instruction with the UIM bits specified.  */
+ #define XX2UIM_MASK (XX2 (0x3f, 0x1ff) | (7 << 18))
+ 
+ /* The mask for an XX2 form instruction with the BF bits specified.  */
+ #define XX2BF_MASK (XX2_MASK | (3 << 21) | (1))
+ 
  /* The mask for an XX3 form instruction.  */
  #define XX3_MASK XX3 (0x3f, 0xff)
  
! /* The mask for an XX3 form instruction with the BF bits specified.  */
! #define XX3BF_MASK (XX3 (0x3f, 0xff) | (3 << 21) | (1))
! 
! /* The mask for an XX3 form instruction with the DM or SHW bits specified.  */
  #define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10))
+ #define XX3SHW_MASK XX3DM_MASK
+ 
+ /* The mask for an XX4 form instruction.  */
+ #define XX4_MASK XX4 (0x3f, 0x3)
+ 
+ /* An X form wait instruction with everything filled in except the WC field.  */
+ #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
  
  /* The mask for a Z form instruction.  */
  #define Z_MASK ZRC (0x3f, 0x1ff, 1)
*************** extract_xb6s (unsigned long insn,
*** 1803,1808 ****
--- 1889,1895 ----
  #define POWER4	PPC_OPCODE_POWER4
  #define POWER5	PPC_OPCODE_POWER5
  #define POWER6	PPC_OPCODE_POWER6
+ #define POWER7	PPC_OPCODE_POWER7
  #define CELL	PPC_OPCODE_CELL
  #define PPC32	PPC_OPCODE_32 | PPC_OPCODE_PPC
  #define PPC64	PPC_OPCODE_64 | PPC_OPCODE_PPC
*************** const struct powerpc_opcode powerpc_opco
*** 3425,3430 ****
--- 3512,3519 ----
  
  {"lvewx",	X(31,71),	X_MASK,      PPCVEC,	PPCNONE,	{VD, RA, RB}},
  
+ {"addg6s",	XO(31,74,0,0),	XO_MASK,     POWER6,	PPCNONE,	{RT, RA, RB}},
+ 
  {"iseleq",	X(31,79),	X_MASK,      PPCISEL,	PPCNONE,	{RT, RA, RB}},
  
  {"isel",	XISEL(31,15),	XISEL_MASK,  PPCISEL,	PPCNONE,	{RT, RA, RB, CRB}},
*************** const struct powerpc_opcode powerpc_opco
*** 3434,3439 ****
--- 3523,3530 ----
  {"subf.",	XO(31,40,0,1),	XO_MASK,     PPC,	PPCNONE,	{RT, RA, RB}},
  {"sub.",	XO(31,40,0,1),	XO_MASK,     PPC,	PPCNONE,	{RT, RB, RA}},
  
+ {"lbarx",	X(31,52),	XEH_MASK,    POWER7,	PPCNONE,	{RT, RA0, RB, EH}},
+ 
  {"ldux",	X(31,53),	X_MASK,      PPC64,	PPCNONE,	{RT, RAL, RB}},
  
  {"dcbst",	X(31,54),	XRT_MASK,    PPC,	PPCNONE,	{RA, RB}},
*************** const struct powerpc_opcode powerpc_opco
*** 3447,3453 ****
  {"andc",	XRC(31,60,0),	X_MASK,      COM,	PPCNONE,	{RA, RS, RB}},
  {"andc.",	XRC(31,60,1),	X_MASK,      COM,	PPCNONE,	{RA, RS, RB}},
  
! {"wait",	X(31,62),	0xffffffff,  E500MC,	PPCNONE,	{0}},
  
  {"dcbstep",	XRT(31,63,0),	XRT_MASK,    E500MC,	PPCNONE,	{RA, RB}},
  
--- 3538,3546 ----
  {"andc",	XRC(31,60,0),	X_MASK,      COM,	PPCNONE,	{RA, RS, RB}},
  {"andc.",	XRC(31,60,1),	X_MASK,      COM,	PPCNONE,	{RA, RS, RB}},
  
! {"waitrsv",	X(31,62)|(1<<21), 0xffffffff, POWER7|E500MC, PPCNONE,	{0}},
! {"waitimpl",	X(31,62)|(2<<21), 0xffffffff, POWER7|E500MC, PPCNONE,	{0}},
! {"wait",	X(31,62),	XWC_MASK, POWER7|E500MC, PPCNONE,	{WC}},
  
  {"dcbstep",	XRT(31,63,0),	XRT_MASK,    E500MC,	PPCNONE,	{RA, RB}},
  
*************** const struct powerpc_opcode powerpc_opco
*** 3501,3506 ****
--- 3594,3601 ----
  
  {"mtsrdin",	X(31,114),	XRA_MASK,    PPC64,	PPCNONE,	{RS, RB}},
  
+ {"lharx",	X(31,116),	XEH_MASK,    POWER7,	PPCNONE,	{RT, RA0, RB, EH}},
+ 
  {"clf",		X(31,118),	XTO_MASK,    POWER,	PPCNONE,	{RA, RB}},
  
  {"lbzux",	X(31,119),	X_MASK,      COM,	PPCNONE,	{RT, RAL, RB}},
*************** const struct powerpc_opcode powerpc_opco
*** 3636,3648 ****
  {"mtsrin",	X(31,242),	XRA_MASK,    PPC32,	PPCNONE,	{RS, RB}},
  {"mtsri",	X(31,242),	XRA_MASK,    POWER32,	PPCNONE,	{RS, RB}},
  
! {"dcbtst",	X(31,246),	X_MASK,      PPC,	PPCNONE,	{CT, RA, RB}},
  
  {"stbux",	X(31,247),	X_MASK,      COM,	PPCNONE,	{RS, RAS, RB}},
  
  {"slliq",	XRC(31,248,0),	X_MASK,      M601,	PPCNONE,	{RA, RS, SH}},
  {"slliq.",	XRC(31,248,1),	X_MASK,      M601,	PPCNONE,	{RA, RS, SH}},
  
  {"dcbtstep",	XRT(31,255,0),	X_MASK,      E500MC,	PPCNONE,	{RT, RA, RB}},
  
  {"mfdcrx",	X(31,259),	X_MASK,      BOOKE,	PPCNONE,	{RS, RA}},
--- 3731,3747 ----
  {"mtsrin",	X(31,242),	XRA_MASK,    PPC32,	PPCNONE,	{RS, RB}},
  {"mtsri",	X(31,242),	XRA_MASK,    POWER32,	PPCNONE,	{RS, RB}},
  
! {"dcbtstt",	XRT(31,246,0x10), XRT_MASK,  POWER7,	PPCNONE,	{RA, RB}},
! {"dcbtst",	X(31,246),	X_MASK,      PPC,	POWER4,		{CT, RA, RB}},
! {"dcbtst",	X(31,246),	X_MASK,      POWER4,	PPCNONE,	{RA, RB, CT}},
  
  {"stbux",	X(31,247),	X_MASK,      COM,	PPCNONE,	{RS, RAS, RB}},
  
  {"slliq",	XRC(31,248,0),	X_MASK,      M601,	PPCNONE,	{RA, RS, SH}},
  {"slliq.",	XRC(31,248,1),	X_MASK,      M601,	PPCNONE,	{RA, RS, SH}},
  
+ {"bpermd",	X(31,252),	X_MASK,      POWER7,	PPCNONE,	{RA, RS, RB}},
+ 
  {"dcbtstep",	XRT(31,255,0),	X_MASK,      E500MC,	PPCNONE,	{RT, RA, RB}},
  
  {"mfdcrx",	X(31,259),	X_MASK,      BOOKE,	PPCNONE,	{RS, RA}},
*************** const struct powerpc_opcode powerpc_opco
*** 3667,3676 ****
  {"lscbx",	XRC(31,277,0),	X_MASK,      M601,	PPCNONE,	{RT, RA, RB}},
  {"lscbx.",	XRC(31,277,1),	X_MASK,      M601,	PPCNONE,	{RT, RA, RB}},
  
! {"dcbt",	X(31,278),	X_MASK,      PPC,	PPCNONE,	{CT, RA, RB}},
  
  {"lhzx",	X(31,279),	X_MASK,      COM,	PPCNONE,	{RT, RA0, RB}},
  
  {"eqv",		XRC(31,284,0),	X_MASK,      COM,	PPCNONE,	{RA, RS, RB}},
  {"eqv.",	XRC(31,284,1),	X_MASK,      COM,	PPCNONE,	{RA, RS, RB}},
  
--- 3766,3779 ----
  {"lscbx",	XRC(31,277,0),	X_MASK,      M601,	PPCNONE,	{RT, RA, RB}},
  {"lscbx.",	XRC(31,277,1),	X_MASK,      M601,	PPCNONE,	{RT, RA, RB}},
  
! {"dcbtt",	XRT(31,278,0x10), XRT_MASK,  POWER7,	PPCNONE,	{RA, RB}},
! {"dcbt",	X(31,278),	X_MASK,      PPC,	POWER4,		{CT, RA, RB}},
! {"dcbt",	X(31,278),	X_MASK,      POWER4,	PPCNONE,	{RA, RB, CT}},
  
  {"lhzx",	X(31,279),	X_MASK,      COM,	PPCNONE,	{RT, RA0, RB}},
  
+ {"cdtbcd",	X(31,282),	XRB_MASK,    POWER6,	PPCNONE,	{RA, RS}},
+ 
  {"eqv",		XRC(31,284,0),	X_MASK,      COM,	PPCNONE,	{RA, RS, RB}},
  {"eqv.",	XRC(31,284,1),	X_MASK,      COM,	PPCNONE,	{RA, RS, RB}},
  
*************** const struct powerpc_opcode powerpc_opco
*** 3685,3690 ****
--- 3788,3795 ----
  
  {"lhzux",	X(31,311),	X_MASK,      COM,	PPCNONE,	{RT, RAL, RB}},
  
+ {"cbcdtd",	X(31,314),	XRB_MASK,    POWER6,	PPCNONE,	{RA, RS}},
+ 
  {"xor",		XRC(31,316,0),	X_MASK,      COM,	PPCNONE,	{RA, RS, RB}},
  {"xor.",	XRC(31,316,1),	X_MASK,      COM,	PPCNONE,	{RA, RS, RB}},
  
*************** const struct powerpc_opcode powerpc_opco
*** 3729,3734 ****
--- 3834,3841 ----
  {"div",		XO(31,331,0,0),	XO_MASK,     M601,	PPCNONE,	{RT, RA, RB}},
  {"div.",	XO(31,331,0,1),	XO_MASK,     M601,	PPCNONE,	{RT, RA, RB}},
  
+ {"lxvdsx",	X(31,332),	XX1_MASK,    PPCVSX,	PPCNONE,	{XT6, RA, RB}},
+ 
  {"mfpmr",	X(31,334),	X_MASK, PPCPMR|PPCE300,	PPCNONE,	{RT, PMR}},
  
  {"mfmq",	XSPR(31,339,  0), XSPR_MASK, M601,	PPCNONE,	{RT}},
*************** const struct powerpc_opcode powerpc_opco
*** 3935,3941 ****
  
  {"mftbl",	XSPR(31,371,268), XSPR_MASK, CLASSIC,	PPCNONE,	{RT}},
  {"mftbu",	XSPR(31,371,269), XSPR_MASK, CLASSIC,	PPCNONE,	{RT}},
! {"mftb",	X(31,371),	X_MASK,      CLASSIC,	PPCNONE,	{RT, TBR}},
  
  {"lwaux",	X(31,373),	X_MASK,      PPC64,	PPCNONE,	{RT, RAL, RB}},
  
--- 4042,4048 ----
  
  {"mftbl",	XSPR(31,371,268), XSPR_MASK, CLASSIC,	PPCNONE,	{RT}},
  {"mftbu",	XSPR(31,371,269), XSPR_MASK, CLASSIC,	PPCNONE,	{RT}},
! {"mftb",	X(31,371),	X_MASK,      CLASSIC,	POWER7,		{RT, TBR}},
  
  {"lwaux",	X(31,373),	X_MASK,      PPC64,	PPCNONE,	{RT, RAL, RB}},
  
*************** const struct powerpc_opcode powerpc_opco
*** 3943,3953 ****
--- 4050,4067 ----
  
  {"lhaux",	X(31,375),	X_MASK,      COM,	PPCNONE,	{RT, RAL, RB}},
  
+ {"popcntw",	X(31,378),	XRB_MASK,    POWER7,	PPCNONE,	{RA, RS}},
+ 
  {"mtdcrx",	X(31,387),	X_MASK,      BOOKE,	PPCNONE,	{RA, RS}},
  
  {"dcblc",	X(31,390),	X_MASK,      PPCCHLK,	PPCNONE,	{CT, RA, RB}},
  {"stdfcmx",	APU(31,391,0), 	APU_MASK,    PPC405,	PPCNONE,	{FCRT, RA, RB}},
  
+ {"divdeu",	XO(31,393,0,0),	XO_MASK,     POWER7,	PPCNONE,	{RT, RA, RB}},
+ {"divdeu.",	XO(31,393,0,1),	XO_MASK,     POWER7,	PPCNONE,	{RT, RA, RB}},
+ {"divweu",	XO(31,395,0,0),	XO_MASK,     POWER7,	PPCNONE,	{RT, RA, RB}},
+ {"divweu.",	XO(31,395,0,1),	XO_MASK,     POWER7,	PPCNONE,	{RT, RA, RB}},
+ 
  {"dcblce",	X(31,398),	X_MASK,      PPCCHLK,	PPCNONE,	{CT, RA, RB}},
  
  {"slbmte",	X(31,402),	XRA_MASK,    PPC64,	PPCNONE,	{RS, RB}},
*************** const struct powerpc_opcode powerpc_opco
*** 3961,3966 ****
--- 4075,4085 ----
  
  {"mtdcrux",	X(31,419),	X_MASK,      PPC464,	PPCNONE,	{RA, RS}},
  
+ {"divde",	XO(31,425,0,0),	XO_MASK,     POWER7,	PPCNONE,	{RT, RA, RB}},
+ {"divde.",	XO(31,425,0,1),	XO_MASK,     POWER7,	PPCNONE,	{RT, RA, RB}},
+ {"divwe",	XO(31,427,0,0),	XO_MASK,     POWER7,	PPCNONE,	{RT, RA, RB}},
+ {"divwe.",	XO(31,427,0,1),	XO_MASK,     POWER7,	PPCNONE,	{RT, RA, RB}},
+ 
  {"slbie",	X(31,434),	XRTRA_MASK,  PPC64,	PPCNONE,	{RB}},
  
  {"ecowx",	X(31,438),	X_MASK,      PPC,	PPCNONE,	{RT, RA, RB}},
*************** const struct powerpc_opcode powerpc_opco
*** 4202,4210 ****
  
  {"cli",		X(31,502),	XRB_MASK,    POWER,	PPCNONE,	{RT, RA}},
  
  {"cmpb",	X(31,508),	X_MASK,      POWER6,	PPCNONE,	{RA, RS, RB}},
  
! {"mcrxr",	X(31,512), XRARB_MASK|(3<<21), COM,	PPCNONE,	{BF}},
  
  {"lbdx",	X(31,515),	X_MASK,      E500MC,	PPCNONE,	{RT, RA, RB}},
  
--- 4321,4331 ----
  
  {"cli",		X(31,502),	XRB_MASK,    POWER,	PPCNONE,	{RT, RA}},
  
+ {"popcntd",	X(31,506),	XRB_MASK,    POWER7,	PPCNONE,	{RA, RS}},
+ 
  {"cmpb",	X(31,508),	X_MASK,      POWER6,	PPCNONE,	{RA, RS, RB}},
  
! {"mcrxr",	X(31,512), XRARB_MASK|(3<<21), COM,	POWER7,		{BF}},
  
  {"lbdx",	X(31,515),	X_MASK,      E500MC,	PPCNONE,	{RT, RA, RB}},
  
*************** const struct powerpc_opcode powerpc_opco
*** 4227,4233 ****
  
  {"clcs",	X(31,531),	XRB_MASK,    M601,	PPCNONE,	{RT, RA}},
  
! {"ldbrx",	X(31,532),	X_MASK,      CELL,	PPCNONE,	{RT, RA0, RB}},
  
  {"lswx",	X(31,533),	X_MASK,      PPCCOM,	PPCNONE,	{RT, RA0, RB}},
  {"lsx",		X(31,533),	X_MASK,      PWRCOM,	PPCNONE,	{RT, RA, RB}},
--- 4348,4354 ----
  
  {"clcs",	X(31,531),	XRB_MASK,    M601,	PPCNONE,	{RT, RA}},
  
! {"ldbrx",	X(31,532),	X_MASK,    CELL|POWER7,	PPCNONE,	{RT, RA0, RB}},
  
  {"lswx",	X(31,533),	X_MASK,      PPCCOM,	PPCNONE,	{RT, RA0, RB}},
  {"lsx",		X(31,533),	X_MASK,      PWRCOM,	PPCNONE,	{RT, RA, RB}},
*************** const struct powerpc_opcode powerpc_opco
*** 4271,4276 ****
--- 4392,4399 ----
  
  {"lwfcmux",	APU(31,583,0), 	APU_MASK,    PPC405,	PPCNONE,	{FCRT, RA, RB}},
  
+ {"lxsdx",	X(31,588),	XX1_MASK,    PPCVSX,	PPCNONE,	{XT6, RA, RB}},
+ 
  {"mfsr",	X(31,595), XRB_MASK|(1<<20), COM32,	PPCNONE,	{RT, SR}},
  
  {"lswi",	X(31,597),	X_MASK,      PPCCOM,	PPCNONE,	{RT, RA0, NB}},
*************** const struct powerpc_opcode powerpc_opco
*** 4284,4291 ****
  
  {"lfdx",	X(31,599),	X_MASK,      COM,	PPCNONE,	{FRT, RA0, RB}},
  
! {"lfdepx",	X(31,607),	X_MASK,      E500MC,	PPCNONE,	{RT, RA, RB}},
! {"mffgpr",	XRC(31,607,0),	XRA_MASK,    POWER6,	PPCNONE,	{FRT, RB}},
  
  {"lddx",	X(31,611),	X_MASK,      E500MC,	PPCNONE,	{RT, RA, RB}},
  
--- 4407,4414 ----
  
  {"lfdx",	X(31,599),	X_MASK,      COM,	PPCNONE,	{FRT, RA0, RB}},
  
! {"lfdepx",	X(31,607),	X_MASK,      E500MC,	PPCNONE,	{FRT, RA, RB}},
! {"mffgpr",	XRC(31,607,0),	XRA_MASK,    POWER6,	POWER7,		{FRT, RB}},
  
  {"lddx",	X(31,611),	X_MASK,      E500MC,	PPCNONE,	{RT, RA, RB}},
  
*************** const struct powerpc_opcode powerpc_opco
*** 4297,4302 ****
--- 4420,4427 ----
  {"mulo",	XO(31,107,1,0),	XO_MASK,     M601,	PPCNONE,	{RT, RA, RB}},
  {"mulo.",	XO(31,107,1,1),	XO_MASK,     M601,	PPCNONE,	{RT, RA, RB}},
  
+ {"lxsdux",	X(31,620),	XX1_MASK,    PPCVSX,	PPCNONE,	{XT6, RA, RB}},
+ 
  {"mfsri",	X(31,627),	X_MASK,      PWRCOM,	PPCNONE,	{RT, RA, RB}},
  
  {"dclst",	X(31,630),	XRB_MASK,    PWRCOM,	PPCNONE,	{RS, RA}},
*************** const struct powerpc_opcode powerpc_opco
*** 4320,4326 ****
  
  {"mfsrin",	X(31,659),	XRA_MASK,    PPC32,	PPCNONE,	{RT, RB}},
  
! {"stdbrx",	X(31,660),	X_MASK,      CELL,	PPCNONE,	{RS, RA0, RB}},
  
  {"stswx",	X(31,661),	X_MASK,      PPCCOM,	PPCNONE,	{RS, RA0, RB}},
  {"stsx",	X(31,661),	X_MASK,      PWRCOM,	PPCNONE,	{RS, RA0, RB}},
--- 4445,4451 ----
  
  {"mfsrin",	X(31,659),	XRA_MASK,    PPC32,	PPCNONE,	{RT, RB}},
  
! {"stdbrx",	X(31,660),	X_MASK,    CELL|POWER7,	PPCNONE,	{RS, RA0, RB}},
  
  {"stswx",	X(31,661),	X_MASK,      PPCCOM,	PPCNONE,	{RS, RA0, RB}},
  {"stsx",	X(31,661),	X_MASK,      PWRCOM,	PPCNONE,	{RS, RA0, RB}},
*************** const struct powerpc_opcode powerpc_opco
*** 4341,4346 ****
--- 4466,4473 ----
  {"stvrx",	X(31,679),	X_MASK,      CELL,	PPCNONE,	{VS, RA0, RB}},
  {"sthfcmux",	APU(31,679,0), 	APU_MASK,    PPC405,	PPCNONE,	{FCRT, RA, RB}},
  
+ {"stbcx.",	XRC(31,694,1),	X_MASK,      POWER7,	PPCNONE,	{RS, RA0, RB}},
+ 
  {"stfsux",	X(31,695),	X_MASK,      COM,	PPCNONE,	{FRS, RAS, RB}},
  
  {"sriq",	XRC(31,696,0),	X_MASK,      M601,	PPCNONE,	{RA, RS, SH}},
*************** const struct powerpc_opcode powerpc_opco
*** 4350,4355 ****
--- 4477,4484 ----
  
  {"stwfcmux",	APU(31,711,0), 	APU_MASK,    PPC405,	PPCNONE,	{FCRT, RA, RB}},
  
+ {"stxsdx",	X(31,716),	XX1_MASK,    PPCVSX,	PPCNONE,	{XS6, RA, RB}},
+ 
  {"subfzeo",	XO(31,200,1,0),	XORB_MASK,   PPCCOM,	PPCNONE,	{RT, RA}},
  {"sfzeo",	XO(31,200,1,0),	XORB_MASK,   PWRCOM,	PPCNONE,	{RT, RA}},
  {"subfzeo.",	XO(31,200,1,1),	XORB_MASK,   PPCCOM,	PPCNONE,	{RT, RA}},
*************** const struct powerpc_opcode powerpc_opco
*** 4363,4368 ****
--- 4492,4499 ----
  {"stswi",	X(31,725),	X_MASK,      PPCCOM,	PPCNONE,	{RS, RA0, NB}},
  {"stsi",	X(31,725),	X_MASK,      PWRCOM,	PPCNONE,	{RS, RA0, NB}},
  
+ {"sthcx.",	XRC(31,726,1),	X_MASK,      POWER7,	PPCNONE,	{RS, RA0, RB}},
+ 
  {"stfdx",	X(31,727),	X_MASK,      COM,	PPCNONE,	{FRS, RA0, RB}},
  
  {"srlq",	XRC(31,728,0),	X_MASK,      M601,	PPCNONE,	{RA, RS, RB}},
*************** const struct powerpc_opcode powerpc_opco
*** 4371,4383 ****
  {"sreq",	XRC(31,729,0),	X_MASK,      M601,	PPCNONE,	{RA, RS, RB}},
  {"sreq.",	XRC(31,729,1),	X_MASK,      M601,	PPCNONE,	{RA, RS, RB}},
  
! {"stfdepx",	X(31,735),	X_MASK,      E500MC,	PPCNONE,	{RS, RA, RB}},
! {"mftgpr",	XRC(31,735,0),	XRA_MASK,    POWER6,	PPCNONE,	{RT, FRB}},
  
  {"stddx",	X(31,739),	X_MASK,      E500MC,	PPCNONE,	{RS, RA, RB}},
  
  {"stqfcmux",	APU(31,743,0), 	APU_MASK,    PPC405,	PPCNONE,	{FCRT, RA, RB}},
  
  {"subfmeo",	XO(31,232,1,0),	XORB_MASK,   PPCCOM,	PPCNONE,	{RT, RA}},
  {"sfmeo",	XO(31,232,1,0),	XORB_MASK,   PWRCOM,	PPCNONE,	{RT, RA}},
  {"subfmeo.",	XO(31,232,1,1),	XORB_MASK,   PPCCOM,	PPCNONE,	{RT, RA}},
--- 4502,4516 ----
  {"sreq",	XRC(31,729,0),	X_MASK,      M601,	PPCNONE,	{RA, RS, RB}},
  {"sreq.",	XRC(31,729,1),	X_MASK,      M601,	PPCNONE,	{RA, RS, RB}},
  
! {"stfdepx",	X(31,735),	X_MASK,      E500MC,	PPCNONE,	{FRS, RA, RB}},
! {"mftgpr",	XRC(31,735,0),	XRA_MASK,    POWER6,	POWER7,		{RT, FRB}},
  
  {"stddx",	X(31,739),	X_MASK,      E500MC,	PPCNONE,	{RS, RA, RB}},
  
  {"stqfcmux",	APU(31,743,0), 	APU_MASK,    PPC405,	PPCNONE,	{FCRT, RA, RB}},
  
+ {"stxsdux",	X(31,748),	XX1_MASK,    PPCVSX,	PPCNONE,	{XS6, RA, RB}},
+ 
  {"subfmeo",	XO(31,232,1,0),	XORB_MASK,   PPCCOM,	PPCNONE,	{RT, RA}},
  {"sfmeo",	XO(31,232,1,0),	XORB_MASK,   PWRCOM,	PPCNONE,	{RT, RA}},
  {"subfmeo.",	XO(31,232,1,1),	XORB_MASK,   PPCCOM,	PPCNONE,	{RT, RA}},
*************** const struct powerpc_opcode powerpc_opco
*** 4415,4420 ****
--- 4548,4555 ----
  {"addo.",	XO(31,266,1,1),	XO_MASK,     PPCCOM,	PPCNONE,	{RT, RA, RB}},
  {"caxo.",	XO(31,266,1,1),	XO_MASK,     PWRCOM,	PPCNONE,	{RT, RA, RB}},
  
+ {"lxvw4x",	X(31,780),	XX1_MASK,    PPCVSX,	PPCNONE,	{XT6, RA, RB}},
+ 
  {"tlbivax",	X(31,786),	XRT_MASK,    BOOKE,	PPCNONE,	{RA, RB}},
  {"tlbilx",	X(31,787),	X_MASK,      E500MC,	PPCNONE,	{T, RA0, RB}},
  {"tlbilxlpid",	XTO(31,787,0),	XTO_MASK,    E500MC,	PPCNONE,	{0}},
*************** const struct powerpc_opcode powerpc_opco
*** 4425,4432 ****
  
  {"lhbrx",	X(31,790),	X_MASK,      COM,	PPCNONE,	{RT, RA0, RB}},
  
  {"lfqx",	X(31,791),	X_MASK,      POWER2,	PPCNONE,	{FRT, RA, RB}},
- {"lfdpx",	X(31,791),	X_MASK,      POWER6,	PPCNONE,	{FRT, RA, RB}},
  
  {"sraw",	XRC(31,792,0),	X_MASK,      PPCCOM,	PPCNONE,	{RA, RS, RB}},
  {"sra",		XRC(31,792,0),	X_MASK,      PWRCOM,	PPCNONE,	{RA, RS, RB}},
--- 4560,4567 ----
  
  {"lhbrx",	X(31,790),	X_MASK,      COM,	PPCNONE,	{RT, RA0, RB}},
  
+ {"lfdpx",	X(31,791),	X_MASK,      POWER6,	POWER7,		{FRT, RA, RB}},
  {"lfqx",	X(31,791),	X_MASK,      POWER2,	PPCNONE,	{FRT, RA, RB}},
  
  {"sraw",	XRC(31,792,0),	X_MASK,      PPCCOM,	PPCNONE,	{RA, RS, RB}},
  {"sra",		XRC(31,792,0),	X_MASK,      PWRCOM,	PPCNONE,	{RA, RS, RB}},
*************** const struct powerpc_opcode powerpc_opco
*** 4440,4445 ****
--- 4575,4582 ----
  
  {"lvrxl",	X(31,807),	X_MASK,      CELL,	PPCNONE,	{VD, RA0, RB}},
  
+ {"lxvw4ux",	X(31,812),	XX1_MASK,    PPCVSX,	PPCNONE,	{XT6, RA, RB}},
+ 
  {"rac",		X(31,818),	X_MASK,      PWRCOM,	PPCNONE,	{RT, RA, RB}},
  
  {"lhzcix",	X(31,821),	X_MASK,      POWER6,	PPCNONE,	{RT, RA0, RB}},
*************** const struct powerpc_opcode powerpc_opco
*** 4480,4488 ****
--- 4617,4634 ----
  
  {"ldcix",	X(31,885),	X_MASK,      POWER6,	PPCNONE,	{RT, RA0, RB}},
  
+ {"lfiwzx",	X(31,887),	X_MASK,      POWER7,	PPCNONE,	{FRT, RA0, RB}},
+ 
  {"stvlxl",	X(31,903),	X_MASK,      CELL,	PPCNONE,	{VS, RA0, RB}},
  {"stdfcmux",	APU(31,903,0), 	APU_MASK,    PPC405,	PPCNONE,	{FCRT, RA, RB}},
  
+ {"divdeuo",	XO(31,393,1,0),	XO_MASK,     POWER7,	PPCNONE,	{RT, RA, RB}},
+ {"divdeuo.",	XO(31,393,1,1),	XO_MASK,     POWER7,	PPCNONE,	{RT, RA, RB}},
+ {"divweuo",	XO(31,395,1,0),	XO_MASK,     POWER7,	PPCNONE,	{RT, RA, RB}},
+ {"divweuo.",	XO(31,395,1,1),	XO_MASK,     POWER7,	PPCNONE,	{RT, RA, RB}},
+ 
+ {"stxvw4x",	X(31,908),	XX1_MASK,    PPCVSX,	PPCNONE,	{XS6, RA, RB}},
+ 
  {"tlbsx",	XRC(31,914,0),	X_MASK,   PPC403|BOOKE,	PPCNONE,	{RTO, RA, RB}},
  {"tlbsx.",	XRC(31,914,1),	X_MASK,   PPC403|BOOKE,	PPCNONE,	{RTO, RA, RB}},
  
*************** const struct powerpc_opcode powerpc_opco
*** 4492,4499 ****
  
  {"sthbrx",	X(31,918),	X_MASK,      COM,	PPCNONE,	{RS, RA0, RB}},
  
- {"stfqx",	X(31,919),	X_MASK,      POWER2,	PPCNONE,	{FRS, RA, RB}},
  {"stfdpx",	X(31,919),	X_MASK,      POWER6,	PPCNONE,	{FRS, RA, RB}},
  
  {"sraq",	XRC(31,920,0),	X_MASK,      M601,	PPCNONE,	{RA, RS, RB}},
  {"sraq.",	XRC(31,920,1),	X_MASK,      M601,	PPCNONE,	{RA, RS, RB}},
--- 4638,4645 ----
  
  {"sthbrx",	X(31,918),	X_MASK,      COM,	PPCNONE,	{RS, RA0, RB}},
  
  {"stfdpx",	X(31,919),	X_MASK,      POWER6,	PPCNONE,	{FRS, RA, RB}},
+ {"stfqx",	X(31,919),	X_MASK,      POWER2,	PPCNONE,	{FRS, RA, RB}},
  
  {"sraq",	XRC(31,920,0),	X_MASK,      M601,	PPCNONE,	{RA, RS, RB}},
  {"sraq.",	XRC(31,920,1),	X_MASK,      M601,	PPCNONE,	{RA, RS, RB}},
*************** const struct powerpc_opcode powerpc_opco
*** 4510,4515 ****
--- 4656,4668 ----
  
  {"stvrxl",	X(31,935),	X_MASK,      CELL,	PPCNONE,	{VS, RA0, RB}},
  
+ {"divdeo",	XO(31,425,1,0),	XO_MASK,     POWER7,	PPCNONE,	{RT, RA, RB}},
+ {"divdeo.",	XO(31,425,1,1),	XO_MASK,     POWER7,	PPCNONE,	{RT, RA, RB}},
+ {"divweo",	XO(31,427,1,0),	XO_MASK,     POWER7,	PPCNONE,	{RT, RA, RB}},
+ {"divweo.",	XO(31,427,1,1),	XO_MASK,     POWER7,	PPCNONE,	{RT, RA, RB}},
+ 
+ {"stxvw4ux",	X(31,940),	XX1_MASK,    PPCVSX,	PPCNONE,	{XS6, RA, RB}},
+ 
  {"tlbrehi",	XTLB(31,946,0),	XTLB_MASK,   PPC403,	PPCNONE,	{RT, RA}},
  {"tlbrelo",	XTLB(31,946,1),	XTLB_MASK,   PPC403,	PPCNONE,	{RT, RA}},
  {"tlbre",	X(31,946),	X_MASK,   PPC403|BOOKE,	PPCNONE,	{RSO, RAOPT, SHO}},
*************** const struct powerpc_opcode powerpc_opco
*** 4648,4659 ****
  
  {"psq_l",	OP(56),		OP_MASK,     PPCPS,	PPCNONE,	{FRT,PSD,RA,PSW,PSQ}},
  
  {"lfqu",	OP(57),		OP_MASK,     POWER2,	PPCNONE,	{FRT, D, RA0}},
  
  {"psq_lu",	OP(57),		OP_MASK,     PPCPS,	PPCNONE,	{FRT,PSD,RA,PSW,PSQ}},
  
- {"lfdp",	OP(57),		OP_MASK,     POWER6,	PPCNONE,	{FRT, D, RA0}},
- 
  {"ld",		DSO(58,0),	DS_MASK,     PPC64,	PPCNONE,	{RT, DS, RA0}},
  {"ldu",		DSO(58,1),	DS_MASK,     PPC64,	PPCNONE,	{RT, DS, RAL}},
  {"lwa",		DSO(58,2),	DS_MASK,     PPC64,	PPCNONE,	{RT, DS, RA0}},
--- 4801,4812 ----
  
  {"psq_l",	OP(56),		OP_MASK,     PPCPS,	PPCNONE,	{FRT,PSD,RA,PSW,PSQ}},
  
+ {"lfdp",	OP(57),		OP_MASK,     POWER6,	POWER7,		{FRT, D, RA0}},
+ 
  {"lfqu",	OP(57),		OP_MASK,     POWER2,	PPCNONE,	{FRT, D, RA0}},
  
  {"psq_lu",	OP(57),		OP_MASK,     PPCPS,	PPCNONE,	{FRT,PSD,RA,PSW,PSQ}},
  
  {"ld",		DSO(58,0),	DS_MASK,     PPC64,	PPCNONE,	{RT, DS, RA0}},
  {"ldu",		DSO(58,1),	DS_MASK,     PPC64,	PPCNONE,	{RT, DS, RAL}},
  {"lwa",		DSO(58,2),	DS_MASK,     PPC64,	PPCNONE,	{RT, DS, RA0}},
*************** const struct powerpc_opcode powerpc_opco
*** 4676,4689 ****
  {"fsqrts",	A(59,22,0),    AFRAFRC_MASK, PPC,	PPCNONE,	{FRT, FRB}},
  {"fsqrts.",	A(59,22,1),    AFRAFRC_MASK, PPC,	PPCNONE,	{FRT, FRB}},
  
! {"fres",	A(59,24,0),   AFRALFRC_MASK, PPC,	PPCNONE,	{FRT, FRB, A_L}},
! {"fres.",	A(59,24,1),   AFRALFRC_MASK, PPC,	PPCNONE,	{FRT, FRB, A_L}},
  
  {"fmuls",	A(59,25,0),	AFRB_MASK,   PPC,	PPCNONE,	{FRT, FRA, FRC}},
  {"fmuls.",	A(59,25,1),	AFRB_MASK,   PPC,	PPCNONE,	{FRT, FRA, FRC}},
  
! {"frsqrtes",	A(59,26,0),   AFRALFRC_MASK, POWER5,	PPCNONE,	{FRT, FRB, A_L}},
! {"frsqrtes.",	A(59,26,1),   AFRALFRC_MASK, POWER5,	PPCNONE,	{FRT, FRB, A_L}},
  
  {"fmsubs",	A(59,28,0),	A_MASK,      PPC,	PPCNONE,	{FRT, FRA, FRC, FRB}},
  {"fmsubs.",	A(59,28,1),	A_MASK,      PPC,	PPCNONE,	{FRT, FRA, FRC, FRB}},
--- 4829,4846 ----
  {"fsqrts",	A(59,22,0),    AFRAFRC_MASK, PPC,	PPCNONE,	{FRT, FRB}},
  {"fsqrts.",	A(59,22,1),    AFRAFRC_MASK, PPC,	PPCNONE,	{FRT, FRB}},
  
! {"fres",	A(59,24,0),   AFRALFRC_MASK, PPC,	POWER7,		{FRT, FRB, A_L}},
! {"fres.",	A(59,24,1),   AFRALFRC_MASK, PPC,	POWER7,		{FRT, FRB, A_L}},
! {"fres",	A(59,24,0),   AFRAFRC_MASK,  POWER7,	PPCNONE,	{FRT, FRB}},
! {"fres.",	A(59,24,1),   AFRAFRC_MASK,  POWER7,	PPCNONE,	{FRT, FRB}},
  
  {"fmuls",	A(59,25,0),	AFRB_MASK,   PPC,	PPCNONE,	{FRT, FRA, FRC}},
  {"fmuls.",	A(59,25,1),	AFRB_MASK,   PPC,	PPCNONE,	{FRT, FRA, FRC}},
  
! {"frsqrtes",	A(59,26,0),   AFRALFRC_MASK, POWER5,	POWER7,		{FRT, FRB, A_L}},
! {"frsqrtes.",	A(59,26,1),   AFRALFRC_MASK, POWER5,	POWER7,		{FRT, FRB, A_L}},
! {"frsqrtes",	A(59,26,0),   AFRAFRC_MASK,  POWER7,	PPCNONE,	{FRT, FRB}},
! {"frsqrtes.",	A(59,26,1),   AFRAFRC_MASK,  POWER7,	PPCNONE,	{FRT, FRB}},
  
  {"fmsubs",	A(59,28,0),	A_MASK,      PPC,	PPCNONE,	{FRT, FRA, FRC, FRB}},
  {"fmsubs.",	A(59,28,1),	A_MASK,      PPC,	PPCNONE,	{FRT, FRA, FRC, FRB}},
*************** const struct powerpc_opcode powerpc_opco
*** 4749,4776 ****
  {"drsp",	XRC(59,770,0),	X_MASK,      POWER6,	PPCNONE,	{FRT, FRB}},
  {"drsp.",	XRC(59,770,1),	X_MASK,      POWER6,	PPCNONE,	{FRT, FRB}},
  
  {"denbcd",	XRC(59,834,0),	X_MASK,      POWER6,	PPCNONE,	{S, FRT, FRB}},
  {"denbcd.",	XRC(59,834,1),	X_MASK,      POWER6,	PPCNONE,	{S, FRT, FRB}},
  
  {"diex",	XRC(59,866,0),	X_MASK,      POWER6,	PPCNONE,	{FRT, FRA, FRB}},
  {"diex.",	XRC(59,866,1),	X_MASK,      POWER6,	PPCNONE,	{FRT, FRA, FRB}},
  
! {"stfq",	OP(60),		OP_MASK,     POWER2,	PPCNONE,	{FRS, D, RA}},
! 
! {"psq_st",	OP(60),		OP_MASK,     PPCPS,	PPCNONE,	{FRS,PSD,RA,PSW,PSQ}},
  
  {"xxmrghd",	XX3(60,10),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
  {"xxmrgld",	XX3(60,10)|(3<<8), XX3_MASK, PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
  {"xxpermdi",	XX3(60,10),	XX3DM_MASK,  PPCVSX,	PPCNONE,	{XT6, XA6, XB6, DM}},
  {"xvmovdp",	XX3(60,240),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6S}},
  {"xvcpsgndp",	XX3(60,240),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
  
! {"psq_stu",	OP(61),		OP_MASK,     PPCPS,	PPCNONE,	{FRS,PSD,RA,PSW,PSQ}},
  
! {"stfqu",	OP(61),		OP_MASK,     POWER2,	PPCNONE,	{FRS, D, RA}},
  
  {"stfdp",	OP(61),		OP_MASK,     POWER6,	PPCNONE,	{FRT, D, RA0}},
  
  {"std",		DSO(62,0),	DS_MASK,     PPC64,	PPCNONE,	{RS, DS, RA0}},
  {"stdu",	DSO(62,1),	DS_MASK,     PPC64,	PPCNONE,	{RS, DS, RAS}},
  {"stq",		DSO(62,2),	DS_MASK,     POWER4,	PPCNONE,	{RSQ, DS, RA0}},
--- 4906,5078 ----
  {"drsp",	XRC(59,770,0),	X_MASK,      POWER6,	PPCNONE,	{FRT, FRB}},
  {"drsp.",	XRC(59,770,1),	X_MASK,      POWER6,	PPCNONE,	{FRT, FRB}},
  
+ {"dcffix",	XRC(59,802,0), X_MASK|FRA_MASK, POWER7,	PPCNONE,	{FRT, FRB}},
+ {"dcffix.",	XRC(59,802,1), X_MASK|FRA_MASK, POWER7,	PPCNONE,	{FRT, FRB}},
+ 
  {"denbcd",	XRC(59,834,0),	X_MASK,      POWER6,	PPCNONE,	{S, FRT, FRB}},
  {"denbcd.",	XRC(59,834,1),	X_MASK,      POWER6,	PPCNONE,	{S, FRT, FRB}},
  
+ {"fcfids",	XRC(59,846,0),	XRA_MASK,    POWER7,	PPCNONE,	{FRT, FRB}},
+ {"fcfids.",	XRC(59,846,1),	XRA_MASK,    POWER7,	PPCNONE,	{FRT, FRB}},
+ 
  {"diex",	XRC(59,866,0),	X_MASK,      POWER6,	PPCNONE,	{FRT, FRA, FRB}},
  {"diex.",	XRC(59,866,1),	X_MASK,      POWER6,	PPCNONE,	{FRT, FRA, FRB}},
  
! {"fcfidus",	XRC(59,974,0),	XRA_MASK,    POWER7,	PPCNONE,	{FRT, FRB}},
! {"fcfidus.",	XRC(59,974,1),	XRA_MASK,    POWER7,	PPCNONE,	{FRT, FRB}},
  
+ {"xxsldwi",	XX3(60,2),	XX3SHW_MASK, PPCVSX,	PPCNONE,	{XT6, XA6, XB6, SHW}},
+ {"xxsel",	XX4(60,3),	XX4_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6, XC6}},
+ {"xxspltd",	XX3(60,10),	XX3DM_MASK,  PPCVSX,	PPCNONE,	{XT6, XA6, XB6S, DMEX}},
  {"xxmrghd",	XX3(60,10),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xxswapd",	XX3(60,10)|(2<<8), XX3_MASK, PPCVSX,	PPCNONE,	{XT6, XA6, XB6S}},
  {"xxmrgld",	XX3(60,10)|(3<<8), XX3_MASK, PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
  {"xxpermdi",	XX3(60,10),	XX3DM_MASK,  PPCVSX,	PPCNONE,	{XT6, XA6, XB6, DM}},
+ {"xxmrghw",	XX3(60,18),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xsadddp",	XX3(60,32),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xsmaddadp",	XX3(60,33),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xscmpudp",	XX3(60,35),	XX3BF_MASK,  PPCVSX,	PPCNONE,	{BF, XA6, XB6}},
+ {"xssubdp",	XX3(60,40),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xsmaddmdp",	XX3(60,41),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xscmpodp",	XX3(60,43),	XX3BF_MASK,  PPCVSX,	PPCNONE,	{BF, XA6, XB6}},
+ {"xsmuldp",	XX3(60,48),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xsmsubadp",	XX3(60,49),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xxmrglw",	XX3(60,50),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xsdivdp",	XX3(60,56),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xsmsubmdp",	XX3(60,57),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xstdivdp",	XX3(60,61),	XX3BF_MASK,  PPCVSX,	PPCNONE,	{BF, XA6, XB6}},
+ {"xvaddsp",	XX3(60,64),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xvmaddasp",	XX3(60,65),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xvcmpeqsp",	XX3RC(60,67,0),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xvcmpeqsp.",	XX3RC(60,67,1),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xvsubsp",	XX3(60,72),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xscvdpuxws",	XX2(60,72),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
+ {"xvmaddmsp",	XX3(60,73),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xsrdpi",	XX2(60,73),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
+ {"xsrsqrtedp",	XX2(60,74),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
+ {"xssqrtdp",	XX2(60,75),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
+ {"xvcmpgtsp",	XX3RC(60,75,0),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xvcmpgtsp.",	XX3RC(60,75,1),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xvmulsp",	XX3(60,80),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xvmsubasp",	XX3(60,81),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xvcmpgesp",	XX3RC(60,83,0),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xvcmpgesp.",	XX3RC(60,83,1),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xvdivsp",	XX3(60,88),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xscvdpsxws",	XX2(60,88),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
+ {"xvmsubmsp",	XX3(60,89),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xsrdpiz",	XX2(60,89),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
+ {"xsredp",	XX2(60,90),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
+ {"xvtdivsp",	XX3(60,93),	XX3BF_MASK,  PPCVSX,	PPCNONE,	{BF, XA6, XB6}},
+ {"xvadddp",	XX3(60,96),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xvmaddadp",	XX3(60,97),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xvcmpeqdp",	XX3RC(60,99,0),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xvcmpeqdp.",	XX3RC(60,99,1),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xvsubdp",	XX3(60,104),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xvmaddmdp",	XX3(60,105),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xsrdpip",	XX2(60,105),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
+ {"xstsqrtdp",	XX2(60,106),	XX2BF_MASK,  PPCVSX,	PPCNONE,	{BF, XB6}},
+ {"xsrdpic",	XX2(60,107),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
+ {"xvcmpgtdp",	XX3RC(60,107,0), XX3_MASK,   PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xvcmpgtdp.",	XX3RC(60,107,1), XX3_MASK,   PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xvmuldp",	XX3(60,112),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xvmsubadp",	XX3(60,113),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xvcmpgedp",	XX3RC(60,115,0), XX3_MASK,   PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xvcmpgedp.",	XX3RC(60,115,1), XX3_MASK,   PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xvdivdp",	XX3(60,120),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xvmsubmdp",	XX3(60,121),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xsrdpim",	XX2(60,121),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
+ {"xvtdivdp",	XX3(60,125),	XX3BF_MASK,  PPCVSX,	PPCNONE,	{BF, XA6, XB6}},
+ {"xxland",	XX3(60,130),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xvcvspuxws",	XX2(60,136),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
+ {"xvrspi",	XX2(60,137),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
+ {"xxlandc",	XX3(60,138),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xvrsqrtesp",	XX2(60,138),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
+ {"xvsqrtsp",	XX2(60,139),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
+ {"xxlor",	XX3(60,146),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xvcvspsxws",	XX2(60,152),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
+ {"xvrspiz",	XX2(60,153),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
+ {"xxlxor",	XX3(60,154),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xvresp",	XX2(60,154),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
+ {"xsmaxdp",	XX3(60,160),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xsnmaddadp",	XX3(60,161),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xxlnor",	XX3(60,162),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xxspltw",	XX2(60,164),	XX2UIM_MASK, PPCVSX,	PPCNONE,	{XT6, XB6, UIM}},
+ {"xsmindp",	XX3(60,168),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xvcvuxwsp",	XX2(60,168),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
+ {"xsnmaddmdp",	XX3(60,169),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xvrspip",	XX2(60,169),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
+ {"xvtsqrtsp",	XX2(60,170),	XX2BF_MASK,  PPCVSX,	PPCNONE,	{BF, XB6}},
+ {"xvrspic",	XX2(60,171),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
+ {"xscpsgndp",	XX3(60,176),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xsnmsubadp",	XX3(60,177),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xvcvsxwsp",	XX2(60,184),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
+ {"xsnmsubmdp",	XX3(60,185),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xvrspim",	XX2(60,185),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
+ {"xvmaxsp",	XX3(60,192),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xvnmaddasp",	XX3(60,193),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xvminsp",	XX3(60,200),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xvcvdpuxws",	XX2(60,200),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
+ {"xvnmaddmsp",	XX3(60,201),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xvrdpi",	XX2(60,201),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
+ {"xvrsqrtedp",	XX2(60,202),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
+ {"xvsqrtdp",	XX2(60,203),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
+ {"xvmovsp",	XX3(60,208),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6S}},
+ {"xvcpsgnsp",	XX3(60,208),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xvnmsubasp",	XX3(60,209),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xvcvdpsxws",	XX2(60,216),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
+ {"xvnmsubmsp",	XX3(60,217),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xvrdpiz",	XX2(60,217),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
+ {"xvredp",	XX2(60,218),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
+ {"xvmaxdp",	XX3(60,224),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xvnmaddadp",	XX3(60,225),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xvmindp",	XX3(60,232),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xvnmaddmdp",	XX3(60,233),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xvcvuxwdp",	XX2(60,232),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
+ {"xvrdpip",	XX2(60,233),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
+ {"xvtsqrtdp",	XX2(60,234),	XX2BF_MASK,  PPCVSX,	PPCNONE,	{BF, XB6}},
+ {"xvrdpic",	XX2(60,235),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
  {"xvmovdp",	XX3(60,240),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6S}},
  {"xvcpsgndp",	XX3(60,240),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xvnmsubadp",	XX3(60,241),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xvcvsxwdp",	XX2(60,248),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
+ {"xvnmsubmdp",	XX3(60,249),	XX3_MASK,    PPCVSX,	PPCNONE,	{XT6, XA6, XB6}},
+ {"xvrdpim",	XX2(60,249),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
+ {"xscvdpsp",	XX2(60,265),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
+ {"xscvdpuxds",	XX2(60,328),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
+ {"xscvspdp",	XX2(60,329),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
+ {"xscvdpsxds",	XX2(60,344),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
+ {"xsabsdp",	XX2(60,345),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
+ {"xscvuxddp",	XX2(60,360),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
+ {"xsnabsdp",	XX2(60,361),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
+ {"xscvsxddp",	XX2(60,376),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
+ {"xsnegdp",	XX2(60,377),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
+ {"xvcvspuxds",	XX2(60,392),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
+ {"xvcvdpsp",	XX2(60,393),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
+ {"xvcvspsxds",	XX2(60,408),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
+ {"xvabssp",	XX2(60,409),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
+ {"xvcvuxdsp",	XX2(60,424),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
+ {"xvnabssp",	XX2(60,425),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
+ {"xvcvsxdsp",	XX2(60,440),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
+ {"xvnegsp",	XX2(60,441),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
+ {"xvcvdpuxds",	XX2(60,456),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
+ {"xvcvspdp",	XX2(60,457),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
+ {"xvcvdpsxds",	XX2(60,472),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
+ {"xvabsdp",	XX2(60,473),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
+ {"xvcvuxddp",	XX2(60,488),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
+ {"xvnabsdp",	XX2(60,489),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
+ {"xvcvsxddp",	XX2(60,504),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
+ {"xvnegdp",	XX2(60,505),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
  
! {"stfq",	OP(60),		OP_MASK,     POWER2,	PPCNONE,	{FRS, D, RA}},
  
! {"psq_st",	OP(60),		OP_MASK,     PPCPS,	PPCNONE,	{FRS,PSD,RA,PSW,PSQ}},
  
  {"stfdp",	OP(61),		OP_MASK,     POWER6,	PPCNONE,	{FRT, D, RA0}},
  
+ {"stfqu",	OP(61),		OP_MASK,     POWER2,	PPCNONE,	{FRS, D, RA}},
+ 
+ {"psq_stu",	OP(61),		OP_MASK,     PPCPS,	PPCNONE,	{FRS,PSD,RA,PSW,PSQ}},
+ 
  {"std",		DSO(62,0),	DS_MASK,     PPC64,	PPCNONE,	{RS, DS, RA0}},
  {"stdu",	DSO(62,1),	DS_MASK,     PPC64,	PPCNONE,	{RS, DS, RAS}},
  {"stq",		DSO(62,2),	DS_MASK,     POWER4,	PPCNONE,	{RSQ, DS, RA0}},
*************** const struct powerpc_opcode powerpc_opco
*** 4820,4835 ****
  {"fsel",	A(63,23,0),	A_MASK,      PPC,	PPCNONE,	{FRT, FRA, FRC, FRB}},
  {"fsel.",	A(63,23,1),	A_MASK,      PPC,	PPCNONE,	{FRT, FRA, FRC, FRB}},
  
! {"fre",		A(63,24,0),   AFRALFRC_MASK, POWER5,	PPCNONE,	{FRT, FRB, A_L}},
! {"fre.",	A(63,24,1),   AFRALFRC_MASK, POWER5,	PPCNONE,	{FRT, FRB, A_L}},
  
  {"fmul",	A(63,25,0),	AFRB_MASK,   PPCCOM,	PPCNONE,	{FRT, FRA, FRC}},
  {"fm",		A(63,25,0),	AFRB_MASK,   PWRCOM,	PPCNONE,	{FRT, FRA, FRC}},
  {"fmul.",	A(63,25,1),	AFRB_MASK,   PPCCOM,	PPCNONE,	{FRT, FRA, FRC}},
  {"fm.",		A(63,25,1),	AFRB_MASK,   PWRCOM,	PPCNONE,	{FRT, FRA, FRC}},
  
! {"frsqrte",	A(63,26,0),   AFRALFRC_MASK, PPC,	PPCNONE,	{FRT, FRB, A_L}},
! {"frsqrte.",	A(63,26,1),   AFRALFRC_MASK, PPC,	PPCNONE,	{FRT, FRB, A_L}},
  
  {"fmsub",	A(63,28,0),	A_MASK,      PPCCOM,	PPCNONE,	{FRT, FRA, FRC, FRB}},
  {"fms",		A(63,28,0),	A_MASK,      PWRCOM,	PPCNONE,	{FRT, FRA, FRC, FRB}},
--- 5122,5141 ----
  {"fsel",	A(63,23,0),	A_MASK,      PPC,	PPCNONE,	{FRT, FRA, FRC, FRB}},
  {"fsel.",	A(63,23,1),	A_MASK,      PPC,	PPCNONE,	{FRT, FRA, FRC, FRB}},
  
! {"fre",		A(63,24,0),   AFRALFRC_MASK, POWER5,	POWER7,		{FRT, FRB, A_L}},
! {"fre.",	A(63,24,1),   AFRALFRC_MASK, POWER5,	POWER7,		{FRT, FRB, A_L}},
! {"fre",		A(63,24,0),   AFRAFRC_MASK,  POWER7,	PPCNONE,	{FRT, FRB}},
! {"fre.",	A(63,24,1),   AFRAFRC_MASK,  POWER7,	PPCNONE,	{FRT, FRB}},
  
  {"fmul",	A(63,25,0),	AFRB_MASK,   PPCCOM,	PPCNONE,	{FRT, FRA, FRC}},
  {"fm",		A(63,25,0),	AFRB_MASK,   PWRCOM,	PPCNONE,	{FRT, FRA, FRC}},
  {"fmul.",	A(63,25,1),	AFRB_MASK,   PPCCOM,	PPCNONE,	{FRT, FRA, FRC}},
  {"fm.",		A(63,25,1),	AFRB_MASK,   PWRCOM,	PPCNONE,	{FRT, FRA, FRC}},
  
! {"frsqrte",	A(63,26,0),   AFRALFRC_MASK, PPC,	POWER7,		{FRT, FRB, A_L}},
! {"frsqrte.",	A(63,26,1),   AFRALFRC_MASK, PPC,	POWER7,		{FRT, FRB, A_L}},
! {"frsqrte",	A(63,26,0),   AFRAFRC_MASK,  POWER7,	PPCNONE,	{FRT, FRB}},
! {"frsqrte.",	A(63,26,1),   AFRAFRC_MASK,  POWER7,	PPCNONE,	{FRT, FRB}},
  
  {"fmsub",	A(63,28,0),	A_MASK,      PPCCOM,	PPCNONE,	{FRT, FRA, FRC, FRB}},
  {"fms",		A(63,28,0),	A_MASK,      PWRCOM,	PPCNONE,	{FRT, FRA, FRC, FRB}},
*************** const struct powerpc_opcode powerpc_opco
*** 4885,4890 ****
--- 5191,5198 ----
  {"drintxq",	ZRC(63,99,0),	Z2_MASK,     POWER6,	PPCNONE,	{R, FRT, FRB, RMC}},
  {"drintxq.",	ZRC(63,99,1),	Z2_MASK,     POWER6,	PPCNONE,	{R, FRT, FRB, RMC}},
  
+ {"ftdiv",	X(63,128),   X_MASK|(3<<21), POWER7,	PPCNONE,	{BF, FRA, FRB}},
+ 
  {"dcmpoq",	X(63,130),	X_MASK,      POWER6,	PPCNONE,	{BF, FRA, FRB}},
  
  {"mtfsfi",  XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, POWER6,	{BFF, U}},
*************** const struct powerpc_opcode powerpc_opco
*** 4895,4900 ****
--- 5203,5215 ----
  {"fnabs",	XRC(63,136,0),	XRA_MASK,    COM,	PPCNONE,	{FRT, FRB}},
  {"fnabs.",	XRC(63,136,1),	XRA_MASK,    COM,	PPCNONE,	{FRT, FRB}},
  
+ {"fctiwu",	XRC(63,142,0),	XRA_MASK,    POWER7,	PPCNONE,	{FRT, FRB}},
+ {"fctiwu.",	XRC(63,142,1),	XRA_MASK,    POWER7,	PPCNONE,	{FRT, FRB}},
+ {"fctiwuz",	XRC(63,143,0),	XRA_MASK,    POWER7,	PPCNONE,	{FRT, FRB}},
+ {"fctiwuz.",	XRC(63,143,1),	XRA_MASK,    POWER7,	PPCNONE,	{FRT, FRB}},
+ 
+ {"ftsqrt",	X(63,160), X_MASK|(3<<21|FRA_MASK), POWER7, PPCNONE,	{BF, FRB}},
+ 
  {"dtstexq",	X(63,162),	X_MASK,      POWER6,	PPCNONE,	{BF, FRA, FRB}},
  {"dtstdcq",	Z(63,194),	Z_MASK,      POWER6,	PPCNONE,	{BF, FRA, DCM}},
  {"dtstdgq",	Z(63,226),	Z_MASK,      POWER6,	PPCNONE,	{BF, FRA, DGM}},
*************** const struct powerpc_opcode powerpc_opco
*** 4965,4970 ****
--- 5280,5293 ----
  {"diexq",	XRC(63,866,0),	X_MASK,      POWER6,	PPCNONE,	{FRT, FRA, FRB}},
  {"diexq.",	XRC(63,866,1),	X_MASK,      POWER6,	PPCNONE,	{FRT, FRA, FRB}},
  
+ {"fctidu",	XRC(63,942,0),	XRA_MASK,    POWER7,	PPCNONE,	{FRT, FRB}},
+ {"fctidu.",	XRC(63,942,1),	XRA_MASK,    POWER7,	PPCNONE,	{FRT, FRB}},
+ 
+ {"fctiduz",	XRC(63,943,0),	XRA_MASK,    POWER7,	PPCNONE,	{FRT, FRB}},
+ {"fctiduz.",	XRC(63,943,1),	XRA_MASK,    POWER7,	PPCNONE,	{FRT, FRB}},
+ 
+ {"fcfidu",	XRC(63,974,0),	XRA_MASK,    POWER7,	PPCNONE,	{FRT, FRB}},
+ {"fcfidu.",	XRC(63,974,1),	XRA_MASK,    POWER7,	PPCNONE,	{FRT, FRB}},
  };
  
  const int powerpc_num_opcodes =