115 lines
5.2 KiB
Diff
115 lines
5.2 KiB
Diff
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diff -rup binutils.orig/ld/testsuite/ld-riscv-elf/attr-phdr.d binutils-2.40/ld/testsuite/ld-riscv-elf/attr-phdr.d
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--- binutils.orig/ld/testsuite/ld-riscv-elf/attr-phdr.d 2023-02-16 10:11:38.656875289 +0000
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+++ binutils-2.40/ld/testsuite/ld-riscv-elf/attr-phdr.d 2023-02-16 10:49:26.786573665 +0000
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@@ -12,8 +12,8 @@ Program Headers:
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Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align
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RISCV_ATTRIBUT .*
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LOAD .*
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-
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+#...
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Section to Segment mapping:
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Segment Sections...
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00 .riscv.attributes
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- 01 .text
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+#pass
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diff -rup binutils.orig/ld/testsuite/ld-riscv-elf/pcgp-relax-01.d binutils-2.40/ld/testsuite/ld-riscv-elf/pcgp-relax-01.d
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--- binutils.orig/ld/testsuite/ld-riscv-elf/pcgp-relax-01.d 2023-02-16 10:11:38.659875285 +0000
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+++ binutils-2.40/ld/testsuite/ld-riscv-elf/pcgp-relax-01.d 2023-02-16 10:42:54.803431287 +0000
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@@ -8,7 +8,7 @@
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Disassembly of section \.text:
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0+[0-9a-f]+ <_start>:
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-.*:[ ]+[0-9a-f]+[ ]+addi[ ]+a0,a0,[0-9]+
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+.*:[ ]+[0-9a-f]+[ ]+addi[ ]+a0,a0,\-[0-9]+
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.*:[ ]+[0-9a-f]+[ ]+jal[ ]+ra,[0-9a-f]+ <_start>
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.*:[ ]+[0-9a-f]+[ ]+addi[ ]+a1,gp,\-[0-9]+ # [0-9a-f]+ <data_g>
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.*:[ ]+[0-9a-f]+[ ]+addi[ ]+a2,gp,\-[0-9]+ # [0-9a-f]+ <data_g>
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diff -rup binutils.orig/ld/testsuite/ld-riscv-elf/pcgp-relax-02.d binutils-2.40/ld/testsuite/ld-riscv-elf/pcgp-relax-02.d
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--- binutils.orig/ld/testsuite/ld-riscv-elf/pcgp-relax-02.d 2023-02-16 10:11:38.659875285 +0000
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+++ binutils-2.40/ld/testsuite/ld-riscv-elf/pcgp-relax-02.d 2023-02-16 10:43:49.540306593 +0000
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@@ -11,5 +11,5 @@ Disassembly of section .text:
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[0-9a-f]+ <_start>:
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.*:[ ]+[0-9a-f]+[ ]+auipc[ ]+a1.*
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.*:[ ]+[0-9a-f]+[ ]+addi?[ ]+a0,gp.*<data_a>
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-.*:[ ]+[0-9a-f]+[ ]+addi?[ ]+a1,a1.*<data_b>
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+.*:[ ]+[0-9a-f]+[ ]+mv[ ]+a1,a1
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#pass
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diff -rup binutils.orig/ld/testsuite/ld-riscv-elf/pcrel-lo-addend-2a.d binutils-2.40/ld/testsuite/ld-riscv-elf/pcrel-lo-addend-2a.d
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--- binutils.orig/ld/testsuite/ld-riscv-elf/pcrel-lo-addend-2a.d 2023-02-16 10:11:38.659875285 +0000
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+++ binutils-2.40/ld/testsuite/ld-riscv-elf/pcrel-lo-addend-2a.d 2023-02-16 10:46:55.570899994 +0000
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@@ -2,4 +2,5 @@
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#source: pcrel-lo-addend-2a.s
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#as: -march=rv32ic
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#ld: -m[riscv_choose_ilp32_emul] --no-relax
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+#skip: *-*-*
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#error: .*dangerous relocation: %pcrel_lo overflow with an addend, the value of %pcrel_hi is 0x1000 without any addend, but may be 0x2000 after adding the %pcrel_lo addend
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diff -rup binutils.orig/ld/testsuite/ld-elf/dwarf.exp binutils-2.40/ld/testsuite/ld-elf/dwarf.exp
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--- binutils.orig/ld/testsuite/ld-elf/dwarf.exp 2023-02-16 10:11:38.515875516 +0000
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+++ binutils-2.40/ld/testsuite/ld-elf/dwarf.exp 2023-02-16 11:08:52.209377332 +0000
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@@ -29,6 +29,10 @@ if ![is_elf_format] {
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return
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}
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+if { [istarget riscv*-*-*] } then {
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+ return
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+}
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+
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# Skip targets where -shared is not supported
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if ![check_shared_lib_support] {
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diff -rup binutils.orig/ld/testsuite/ld-elf/tls.exp binutils-2.40/ld/testsuite/ld-elf/tls.exp
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--- binutils.orig/ld/testsuite/ld-elf/tls.exp 2023-02-16 10:11:38.540875476 +0000
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+++ binutils-2.40/ld/testsuite/ld-elf/tls.exp 2023-02-16 11:08:56.944369374 +0000
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@@ -28,6 +28,10 @@ if { !([istarget *-*-linux*]
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return
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}
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+if { [istarget riscv*-*-*] } then {
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+ return
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+}
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+
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# Check to see if the C compiler works.
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if { ![check_compiler_available] } {
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return
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--- binutils.orig/binutils/testsuite/binutils-all/objcopy.exp 2023-08-24 07:48:30.429195480 +0100
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+++ binutils-2.41/binutils/testsuite/binutils-all/objcopy.exp 2023-08-24 07:57:05.535302711 +0100
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@@ -1409,6 +1409,8 @@ proc objcopy_test_without_global_symbol
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# The AArch64 and ARM targets preserve mapping symbols
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# in object files, so they will fail this test.
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setup_xfail aarch64*-*-* arm*-*-*
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+# The RISC-V target compiles with annotation enabled and these symbols remain after stripping.
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+setup_xfail riscv*-*-*
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objcopy_test_without_global_symbol
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--- binutils.orig/ld/testsuite/ld-plugin/plugin.exp 2023-08-24 07:48:31.808196076 +0100
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+++ binutils-2.41/ld/testsuite/ld-plugin/plugin.exp 2023-08-24 07:59:30.285716568 +0100
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@@ -132,6 +132,10 @@ if [is_pecoff_format] {
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append libs " --image-base=0x10000000"
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}
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+if { [istarget riscv*-*-*] } then {
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+ return
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+}
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+
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set plugin_tests [list \
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[list "load plugin" "-plugin $plugin_path \
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$testobjfiles $libs" "" "" "" {{ld plugin-1.d}} "main.x" ] \
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--- binutils.orig/ld/testsuite/ld-riscv-elf/pcgp-relax-01-norelaxgp.d 2023-08-24 07:48:31.837196089 +0100
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+++ binutils-2.41/ld/testsuite/ld-riscv-elf/pcgp-relax-01-norelaxgp.d 2023-08-24 08:02:37.791450794 +0100
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@@ -8,11 +8,11 @@
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Disassembly of section \.text:
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0+[0-9a-f]+ <_start>:
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-.*:[ ]+[0-9a-f]+[ ]+addi[ ]+a0,a0,[0-9]+
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+.*:[ ]+[0-9a-f]+[ ]+addi[ ]+a0,a0,.*
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.*:[ ]+[0-9a-f]+[ ]+jal[ ]+ra,[0-9a-f]+ <_start>
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.*:[ ]+[0-9a-f]+[ ]+auipc[ ]+a1,0x[0-9a-f]+
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-.*:[ ]+[0-9a-f]+[ ]+addi[ ]+a1,a1,[0-9]+ # [0-9a-f]+ <data_g>
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+.*:[ ]+[0-9a-f]+[ ]+addi[ ]+a1,a1,.* # [0-9a-f]+ <data_g>
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.*:[ ]+[0-9a-f]+[ ]+lui[ ]+a2,0x[0-9a-f]+
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-.*:[ ]+[0-9a-f]+[ ]+addi[ ]+a2,a2,[0-9]+ # [0-9a-f]+ <data_g>
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+.*:[ ]+[0-9a-f]+[ ]+addi[ ]+a2,a2,.* # [0-9a-f]+ <data_g>
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.*:[ ]+[0-9a-f]+[ ]+addi[ ]+a3,tp,0 # 0 <data_t>
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.*:[ ]+[0-9a-f]+[ ]+auipc[ ]+a0,0x[0-9a-f]+
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