222 lines
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222 lines
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([fe80::1454:87a:13b0:d3a%7]) with mapi id 15.20.2387.019; Wed, 23 Oct 2019
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07:30:18 +0000
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From: Anup Patel <Anup.Patel@wdc.com>
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To: Atish Patra <Atish.Patra@wdc.com>, Alistair Francis
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<Alistair.Francis@wdc.com>
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Subject: [PATCH] firmware: Fix compile error for FW_PAYLOAD with latest GCC
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binutils
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Thread-Topic: [PATCH] firmware: Fix compile error for FW_PAYLOAD with latest
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GCC binutils
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Date: Wed, 23 Oct 2019 07:30:18 +0000
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Cc: David Abdurachmanov <david.abdurachmanov@sifive.com>,
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Damien Le Moal <Damien.LeMoal@wdc.com>, Anup Patel <Anup.Patel@wdc.com>,
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"opensbi@lists.infradead.org" <opensbi@lists.infradead.org>
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Errors-To: opensbi-bounces+david.abdurachmanov=gmail.com@lists.infradead.org
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We get following compile error for FW_PAYLOAD with latest GCC
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binutils:
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fw_payload.o(.text+0x1961): 15 bytes required for alignment to 16-byte
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boundary, but only 14 present
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Further investigating, it turn-out to be a known issue with RISC-V
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GCC binutils.
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(Refer, https://github.com/riscv/riscv-gnu-toolchain/issues/298)
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As a work-around, we disable relaxation when including DTB and
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PAYLOAD binary in fw_payload.S.
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Reported-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
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Signed-off-by: Anup Patel <anup.patel@wdc.com>
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---
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firmware/fw_payload.S | 10 ++++++++++
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1 file changed, 10 insertions(+)
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diff --git a/firmware/fw_payload.S b/firmware/fw_payload.S
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index 4b4527a..e873f75 100644
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--- a/firmware/fw_payload.S
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+++ b/firmware/fw_payload.S
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@@ -85,6 +85,14 @@ fw_options:
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add a0, zero, zero
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ret
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+ /*
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+ * We disable relaxation because use of ".align"
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+ * and ".balign" can potentially generate compile
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+ * errors with latest RISC-V GCC Binutils.
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+ */
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+ .option push
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+ .option norelax
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+
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#ifdef FW_PAYLOAD_FDT_PATH
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.align 4
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.section .text, "ax", %progbits
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@@ -103,3 +111,5 @@ payload_bin:
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#else
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.incbin FW_PAYLOAD_PATH
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#endif
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+
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+.option pop
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--
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2.17.1
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_______________________________________________
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opensbi mailing list
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opensbi@lists.infradead.org
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http://lists.infradead.org/mailman/listinfo/opensbi
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