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Wed, 23 Oct 2019 07:30:18 +0000 From: Anup Patel To: Atish Patra , Alistair Francis Subject: [PATCH] firmware: Fix compile error for FW_PAYLOAD with latest GCC binutils Thread-Topic: [PATCH] firmware: Fix compile error for FW_PAYLOAD with latest GCC binutils Thread-Index: AQHViXO4+JD6Bfi5lEyv6PJbDcYIog== Date: Wed, 23 Oct 2019 07:30:18 +0000 Message-ID: <20191023072955.32016-1-anup.patel@wdc.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: MA1PR01CA0091.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00::31) To MN2PR04MB6061.namprd04.prod.outlook.com (2603:10b6:208:d8::15) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Anup.Patel@wdc.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [129.253.179.161] x-ms-publictraffictype: Email x-ms-office365-filtering-ht: Tenant x-ms-office365-filtering-correlation-id: f9cea0bf-ccf8-4b59-b385-08d7578adaab x-ms-traffictypediagnostic: MN2PR04MB6000: x-ms-exchange-purlcount: 1 x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: wdcipoutbound: EOP-TRUE x-ms-oob-tlc-oobclassifiers: OLM:6430; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "opensbi" Errors-To: opensbi-bounces+david.abdurachmanov=gmail.com@lists.infradead.org We get following compile error for FW_PAYLOAD with latest GCC binutils: fw_payload.o(.text+0x1961): 15 bytes required for alignment to 16-byte boundary, but only 14 present Further investigating, it turn-out to be a known issue with RISC-V GCC binutils. (Refer, https://github.com/riscv/riscv-gnu-toolchain/issues/298) As a work-around, we disable relaxation when including DTB and PAYLOAD binary in fw_payload.S. Reported-by: David Abdurachmanov Signed-off-by: Anup Patel --- firmware/fw_payload.S | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/firmware/fw_payload.S b/firmware/fw_payload.S index 4b4527a..e873f75 100644 --- a/firmware/fw_payload.S +++ b/firmware/fw_payload.S @@ -85,6 +85,14 @@ fw_options: add a0, zero, zero ret + /* + * We disable relaxation because use of ".align" + * and ".balign" can potentially generate compile + * errors with latest RISC-V GCC Binutils. + */ + .option push + .option norelax + #ifdef FW_PAYLOAD_FDT_PATH .align 4 .section .text, "ax", %progbits @@ -103,3 +111,5 @@ payload_bin: #else .incbin FW_PAYLOAD_PATH #endif + +.option pop -- 2.17.1 _______________________________________________ opensbi mailing list opensbi@lists.infradead.org http://lists.infradead.org/mailman/listinfo/opensbi