Rebuild (new kernel, U-Boot, OpenSBI revision) + enable L2 for FU540

Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
This commit is contained in:
David Abdurachmanov 2019-11-13 16:55:21 +02:00
parent 05d9fd5f68
commit 9ae42883b8
Signed by: davidlt
GPG Key ID: 8B7F1DA0E2C9FDBB
5 changed files with 265 additions and 225 deletions

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From: Anup Patel <Anup.Patel@wdc.com>
To: Atish Patra <Atish.Patra@wdc.com>, Alistair Francis
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Subject: [PATCH] firmware: Fix compile error for FW_PAYLOAD with latest GCC
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Thread-Topic: [PATCH] firmware: Fix compile error for FW_PAYLOAD with latest
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Cc: David Abdurachmanov <david.abdurachmanov@sifive.com>,
Damien Le Moal <Damien.LeMoal@wdc.com>, Anup Patel <Anup.Patel@wdc.com>,
"opensbi@lists.infradead.org" <opensbi@lists.infradead.org>
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We get following compile error for FW_PAYLOAD with latest GCC
binutils:
fw_payload.o(.text+0x1961): 15 bytes required for alignment to 16-byte
boundary, but only 14 present
Further investigating, it turn-out to be a known issue with RISC-V
GCC binutils.
(Refer, https://github.com/riscv/riscv-gnu-toolchain/issues/298)
As a work-around, we disable relaxation when including DTB and
PAYLOAD binary in fw_payload.S.
Reported-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
firmware/fw_payload.S | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/firmware/fw_payload.S b/firmware/fw_payload.S
index 4b4527a..e873f75 100644
--- a/firmware/fw_payload.S
+++ b/firmware/fw_payload.S
@@ -85,6 +85,14 @@ fw_options:
add a0, zero, zero
ret
+ /*
+ * We disable relaxation because use of ".align"
+ * and ".balign" can potentially generate compile
+ * errors with latest RISC-V GCC Binutils.
+ */
+ .option push
+ .option norelax
+
#ifdef FW_PAYLOAD_FDT_PATH
.align 4
.section .text, "ax", %progbits
@@ -103,3 +111,5 @@ payload_bin:
#else
.incbin FW_PAYLOAD_PATH
#endif
+
+.option pop
--
2.17.1
_______________________________________________
opensbi mailing list
opensbi@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/opensbi

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@ -4,8 +4,8 @@
Name: opensbi-unstable
# The last part is short hash
# Format: <TAG>.<NUMBER_OF_COMMITS_AFTER_TAG>.<YEAR>.<MONTH>.<DAY>.<SHORT_COMMIT>
Version: v0.5.0.2019.10.09.be92da2
Release: 10%{?dist}
Version: v0.5.0.2019.11.13.18897aa
Release: 1%{?dist}
Summary: RISC-V Open Source Supervisor Binary Interface
License: BSD
@ -13,10 +13,10 @@ URL: https://github.com/riscv/opensbi
# Download tarball, e.g.:
# https://github.com/riscv/opensbi/archive/%full_commit.tar.gz
%global full_commit be92da280d87c38a2e0adc5d3f43bab7b5468f09
%global full_commit 18897aaf5d0382017c05a5690d0bc8e0d044270f
Source0: https://github.com/riscv/opensbi/archive/%{full_commit}.tar.gz
Patch0: 0001-fw_payload.S-allow-FDT-payload-where-size-is-not-16-.patch
Patch0: platform-enable-all-l2-cache-ways-for-sifive-fu540-by-default-v2.patch
BuildRequires: systemd-udev
BuildRequires: grubby-deprecated
@ -207,6 +207,12 @@ popd
/boot/opensbi/unstable/fw_payload-uboot-sifive-fu540.{bin,elf}
%changelog
* Wed Nov 13 2019 David Abdurachmanov <david.abdurachmanov@sifive.com> v0.5.0.2019.11.13.18897aa-1
- New OpenSBI revision
- New kernel
- New U-Boot
- Incl. a patch to enable all L2 ways on SiFive FU540 (final patch will be in FSBL)
* Wed Oct 30 2019 David Abdurachmanov <david.abdurachmanov@sifive.com> v0.5.0.2019.10.09.be92da2-10
- Rebuild for new U-Boot

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From: Vincent Chen <vincent.chen@sifive.com>
To: opensbi@lists.infradead.org
Subject: [PATCH v2] platform: Enable all L2 cache ways for sifive fu540 by
default
Date: Tue, 5 Nov 2019 14:46:01 +0800
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Some bootloaders don't enable the entire cache on boot. To avoid
performance degradation, the entire L2 cache should be enabled by
default. If needed, the user can specify the enabled cache
way number via the macro FU540_CCACHE_ENABLEWAY_NUM.
Chnages from v1->v2
1. Corrected the typo in the macro FU540_CCR_WAY_MASK definition
2. Added/Removed empty line.
Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
---
docs/platform/sifive_fu540.md | 18 ++++++++++++++++++
platform/sifive/fu540/objects.mk | 3 +++
platform/sifive/fu540/platform.c | 22 ++++++++++++++++++++++
3 files changed, 43 insertions(+)
diff --git a/docs/platform/sifive_fu540.md b/docs/platform/sifive_fu540.md
index 9fb45d6..63f0b94 100644
--- a/docs/platform/sifive_fu540.md
+++ b/docs/platform/sifive_fu540.md
@@ -13,6 +13,7 @@ To build platform specific library and firmwares, provide the
Platform Options
----------------
+1. *FU540_ENABLED_HART_MASK*
As hart0 in the FU540 doesn't have an MMU, only harts 1-4 boot by default.
A hart mask i.e. *FU540_ENABLED_HART_MASK* compile time option is provided
to select any other hart for booting. Please keep in mind that this is not
@@ -24,6 +25,23 @@ make PLATFORM=sifive/fu540 FW_PAYLOAD_PATH=Image FU540_ENABLED_HART_MASK=0x02
```
This will let the board boot only hart1 instead of default 1-4.
+2. *FU540_CCACHE_ENABLEWAY_NUM*
+FU540 L2 cache controller offers extensive flexibility as it allows for several
+features in addition to the L2 Cache functionality, such as memory-mapped
+access to L2 Cache RAM for disabled cache ways and scratchpad functionality.
+Out of reset, all ways, except for way 0, are disabled. Cache ways can be
+enabled via the L2 controller register. By default, OpenSBI will enable all
+cache ways. If needed, the enabled cache way number can be specified by the
+following command:
+
+```
+make PLATFORM=sifive/fu540 FW_PAYLOAD_PATH=Image FU540_CCACHE_ENABLEWAY_NUM=0x5
+```
+This will enable the way 1 through way 5. Please keep in mind that once a cache
+way is enabled, it can not be disabled unless the FU540-C000 is reset. In other
+words, the macro FU540_CCACHE_ENABLEWAY_NUM cannot disable the ways enabled by
+FSBL or other bootloaders.
+
Building SiFive Fu540 Platform
-----------------------------
diff --git a/platform/sifive/fu540/objects.mk b/platform/sifive/fu540/objects.mk
index f09a305..3f730ad 100644
--- a/platform/sifive/fu540/objects.mk
+++ b/platform/sifive/fu540/objects.mk
@@ -11,3 +11,6 @@ platform-objs-y += platform.o
ifdef FU540_ENABLED_HART_MASK
platform-genflags-y += -DFU540_ENABLED_HART_MASK=$(FU540_ENABLED_HART_MASK)
endif
+ifdef FU540_CCACHE_ENABLEWAY_NUM
+platform-genflags-y += -DFU540_CCACHE_ENABLEWAY_NUM=$(FU540_CCACHE_ENABLEWAY_NUM)
+endif
diff --git a/platform/sifive/fu540/platform.c b/platform/sifive/fu540/platform.c
index 81e8e8d..974cc44 100644
--- a/platform/sifive/fu540/platform.c
+++ b/platform/sifive/fu540/platform.c
@@ -36,6 +36,13 @@
#define FU540_UART1_ADDR 0x10011000
#define FU540_UART_BAUDRATE 115200
+#define FU540_CCACHE_CONTROLLER_ADDR 0x02010000
+#define FU540_CCACHE_CONFIG_REG_OFF 0x0
+#define FU540_CCACHE_WAYENABLE_REG_OFF 0x8
+
+/* FU540 Cache Configuration Register */
+#define FU540_CCR_WAY_BIT_OFF 0x8
+#define FU540_CCR_WAY_MASK (0xff << FU540_CCR_WAY_BIT_OFF)
/**
* The FU540 SoC has 5 HARTs but HART ID 0 doesn't have S mode. enable only
* HARTs 1 to 4.
@@ -88,6 +95,20 @@ static void fu540_modify_dt(void *fdt)
plic_fdt_fixup(fdt, "riscv,plic0");
}
+static void fu540_ccache_init(void)
+{
+ /* By default, enable all L2 cache ways */
+ int l2c_way = (readl((volatile void *)(FU540_CCACHE_CONTROLLER_ADDR +
+ FU540_CCACHE_CONFIG_REG_OFF)) & FU540_CCR_WAY_MASK) >>
+ FU540_CCR_WAY_BIT_OFF;
+#ifdef FU540_CCACHE_ENABLEWAY_NUM
+ if (FU540_CCACHE_ENABLEWAY_NUM < l2c_way)
+ l2c_way = FU540_CCACHE_ENABLEWAY_NUM;
+#endif
+ writeb((char)l2c_way,
+ (void *)(FU540_CCACHE_CONTROLLER_ADDR + FU540_CCACHE_WAYENABLE_REG_OFF));
+}
+
static int fu540_final_init(bool cold_boot)
{
void *fdt;
@@ -95,6 +116,7 @@ static int fu540_final_init(bool cold_boot)
if (!cold_boot)
return 0;
+ fu540_ccache_init();
fdt = sbi_scratch_thishart_arg1_ptr();
fu540_modify_dt(fdt);
--
2.7.4
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