Rebuild (new kernel, U-Boot, OpenSBI revision) + enable L2 for FU540
Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
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From: Anup Patel <Anup.Patel@wdc.com>
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To: Atish Patra <Atish.Patra@wdc.com>, Alistair Francis
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<Alistair.Francis@wdc.com>
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Subject: [PATCH] firmware: Fix compile error for FW_PAYLOAD with latest GCC
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binutils
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Thread-Topic: [PATCH] firmware: Fix compile error for FW_PAYLOAD with latest
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GCC binutils
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Cc: David Abdurachmanov <david.abdurachmanov@sifive.com>,
|
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Damien Le Moal <Damien.LeMoal@wdc.com>, Anup Patel <Anup.Patel@wdc.com>,
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We get following compile error for FW_PAYLOAD with latest GCC
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binutils:
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fw_payload.o(.text+0x1961): 15 bytes required for alignment to 16-byte
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boundary, but only 14 present
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Further investigating, it turn-out to be a known issue with RISC-V
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GCC binutils.
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(Refer, https://github.com/riscv/riscv-gnu-toolchain/issues/298)
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As a work-around, we disable relaxation when including DTB and
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PAYLOAD binary in fw_payload.S.
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Reported-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
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Signed-off-by: Anup Patel <anup.patel@wdc.com>
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---
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firmware/fw_payload.S | 10 ++++++++++
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1 file changed, 10 insertions(+)
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diff --git a/firmware/fw_payload.S b/firmware/fw_payload.S
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index 4b4527a..e873f75 100644
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--- a/firmware/fw_payload.S
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+++ b/firmware/fw_payload.S
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@@ -85,6 +85,14 @@ fw_options:
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add a0, zero, zero
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ret
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+ /*
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+ * We disable relaxation because use of ".align"
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+ * and ".balign" can potentially generate compile
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+ * errors with latest RISC-V GCC Binutils.
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+ */
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+ .option push
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+ .option norelax
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+
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#ifdef FW_PAYLOAD_FDT_PATH
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.align 4
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.section .text, "ax", %progbits
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@@ -103,3 +111,5 @@ payload_bin:
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#else
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.incbin FW_PAYLOAD_PATH
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#endif
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+
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+.option pop
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--
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2.17.1
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_______________________________________________
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@ -4,8 +4,8 @@
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Name: opensbi-unstable
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# The last part is short hash
|
||||
# Format: <TAG>.<NUMBER_OF_COMMITS_AFTER_TAG>.<YEAR>.<MONTH>.<DAY>.<SHORT_COMMIT>
|
||||
Version: v0.5.0.2019.10.09.be92da2
|
||||
Release: 10%{?dist}
|
||||
Version: v0.5.0.2019.11.13.18897aa
|
||||
Release: 1%{?dist}
|
||||
Summary: RISC-V Open Source Supervisor Binary Interface
|
||||
|
||||
License: BSD
|
||||
@ -13,10 +13,10 @@ URL: https://github.com/riscv/opensbi
|
||||
|
||||
# Download tarball, e.g.:
|
||||
# https://github.com/riscv/opensbi/archive/%full_commit.tar.gz
|
||||
%global full_commit be92da280d87c38a2e0adc5d3f43bab7b5468f09
|
||||
%global full_commit 18897aaf5d0382017c05a5690d0bc8e0d044270f
|
||||
Source0: https://github.com/riscv/opensbi/archive/%{full_commit}.tar.gz
|
||||
|
||||
Patch0: 0001-fw_payload.S-allow-FDT-payload-where-size-is-not-16-.patch
|
||||
Patch0: platform-enable-all-l2-cache-ways-for-sifive-fu540-by-default-v2.patch
|
||||
|
||||
BuildRequires: systemd-udev
|
||||
BuildRequires: grubby-deprecated
|
||||
@ -207,6 +207,12 @@ popd
|
||||
/boot/opensbi/unstable/fw_payload-uboot-sifive-fu540.{bin,elf}
|
||||
|
||||
%changelog
|
||||
* Wed Nov 13 2019 David Abdurachmanov <david.abdurachmanov@sifive.com> v0.5.0.2019.11.13.18897aa-1
|
||||
- New OpenSBI revision
|
||||
- New kernel
|
||||
- New U-Boot
|
||||
- Incl. a patch to enable all L2 ways on SiFive FU540 (final patch will be in FSBL)
|
||||
|
||||
* Wed Oct 30 2019 David Abdurachmanov <david.abdurachmanov@sifive.com> v0.5.0.2019.10.09.be92da2-10
|
||||
- Rebuild for new U-Boot
|
||||
|
||||
|
@ -0,0 +1,255 @@
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Mon, 04 Nov 2019 22:46:17 -0800 (PST)
|
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From: Vincent Chen <vincent.chen@sifive.com>
|
||||
To: opensbi@lists.infradead.org
|
||||
Subject: [PATCH v2] platform: Enable all L2 cache ways for sifive fu540 by
|
||||
default
|
||||
Date: Tue, 5 Nov 2019 14:46:01 +0800
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Cc: Vincent Chen <vincent.chen@sifive.com>
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|
||||
|
||||
Some bootloaders don't enable the entire cache on boot. To avoid
|
||||
performance degradation, the entire L2 cache should be enabled by
|
||||
default. If needed, the user can specify the enabled cache
|
||||
way number via the macro FU540_CCACHE_ENABLEWAY_NUM.
|
||||
|
||||
Chnages from v1->v2
|
||||
1. Corrected the typo in the macro FU540_CCR_WAY_MASK definition
|
||||
2. Added/Removed empty line.
|
||||
|
||||
|
||||
Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
|
||||
---
|
||||
docs/platform/sifive_fu540.md | 18 ++++++++++++++++++
|
||||
platform/sifive/fu540/objects.mk | 3 +++
|
||||
platform/sifive/fu540/platform.c | 22 ++++++++++++++++++++++
|
||||
3 files changed, 43 insertions(+)
|
||||
|
||||
diff --git a/docs/platform/sifive_fu540.md b/docs/platform/sifive_fu540.md
|
||||
index 9fb45d6..63f0b94 100644
|
||||
--- a/docs/platform/sifive_fu540.md
|
||||
+++ b/docs/platform/sifive_fu540.md
|
||||
@@ -13,6 +13,7 @@ To build platform specific library and firmwares, provide the
|
||||
Platform Options
|
||||
----------------
|
||||
|
||||
+1. *FU540_ENABLED_HART_MASK*
|
||||
As hart0 in the FU540 doesn't have an MMU, only harts 1-4 boot by default.
|
||||
A hart mask i.e. *FU540_ENABLED_HART_MASK* compile time option is provided
|
||||
to select any other hart for booting. Please keep in mind that this is not
|
||||
@@ -24,6 +25,23 @@ make PLATFORM=sifive/fu540 FW_PAYLOAD_PATH=Image FU540_ENABLED_HART_MASK=0x02
|
||||
```
|
||||
This will let the board boot only hart1 instead of default 1-4.
|
||||
|
||||
+2. *FU540_CCACHE_ENABLEWAY_NUM*
|
||||
+FU540 L2 cache controller offers extensive flexibility as it allows for several
|
||||
+features in addition to the L2 Cache functionality, such as memory-mapped
|
||||
+access to L2 Cache RAM for disabled cache ways and scratchpad functionality.
|
||||
+Out of reset, all ways, except for way 0, are disabled. Cache ways can be
|
||||
+enabled via the L2 controller register. By default, OpenSBI will enable all
|
||||
+cache ways. If needed, the enabled cache way number can be specified by the
|
||||
+following command:
|
||||
+
|
||||
+```
|
||||
+make PLATFORM=sifive/fu540 FW_PAYLOAD_PATH=Image FU540_CCACHE_ENABLEWAY_NUM=0x5
|
||||
+```
|
||||
+This will enable the way 1 through way 5. Please keep in mind that once a cache
|
||||
+way is enabled, it can not be disabled unless the FU540-C000 is reset. In other
|
||||
+words, the macro FU540_CCACHE_ENABLEWAY_NUM cannot disable the ways enabled by
|
||||
+FSBL or other bootloaders.
|
||||
+
|
||||
Building SiFive Fu540 Platform
|
||||
-----------------------------
|
||||
|
||||
diff --git a/platform/sifive/fu540/objects.mk b/platform/sifive/fu540/objects.mk
|
||||
index f09a305..3f730ad 100644
|
||||
--- a/platform/sifive/fu540/objects.mk
|
||||
+++ b/platform/sifive/fu540/objects.mk
|
||||
@@ -11,3 +11,6 @@ platform-objs-y += platform.o
|
||||
ifdef FU540_ENABLED_HART_MASK
|
||||
platform-genflags-y += -DFU540_ENABLED_HART_MASK=$(FU540_ENABLED_HART_MASK)
|
||||
endif
|
||||
+ifdef FU540_CCACHE_ENABLEWAY_NUM
|
||||
+platform-genflags-y += -DFU540_CCACHE_ENABLEWAY_NUM=$(FU540_CCACHE_ENABLEWAY_NUM)
|
||||
+endif
|
||||
diff --git a/platform/sifive/fu540/platform.c b/platform/sifive/fu540/platform.c
|
||||
index 81e8e8d..974cc44 100644
|
||||
--- a/platform/sifive/fu540/platform.c
|
||||
+++ b/platform/sifive/fu540/platform.c
|
||||
@@ -36,6 +36,13 @@
|
||||
#define FU540_UART1_ADDR 0x10011000
|
||||
#define FU540_UART_BAUDRATE 115200
|
||||
|
||||
+#define FU540_CCACHE_CONTROLLER_ADDR 0x02010000
|
||||
+#define FU540_CCACHE_CONFIG_REG_OFF 0x0
|
||||
+#define FU540_CCACHE_WAYENABLE_REG_OFF 0x8
|
||||
+
|
||||
+/* FU540 Cache Configuration Register */
|
||||
+#define FU540_CCR_WAY_BIT_OFF 0x8
|
||||
+#define FU540_CCR_WAY_MASK (0xff << FU540_CCR_WAY_BIT_OFF)
|
||||
/**
|
||||
* The FU540 SoC has 5 HARTs but HART ID 0 doesn't have S mode. enable only
|
||||
* HARTs 1 to 4.
|
||||
@@ -88,6 +95,20 @@ static void fu540_modify_dt(void *fdt)
|
||||
plic_fdt_fixup(fdt, "riscv,plic0");
|
||||
}
|
||||
|
||||
+static void fu540_ccache_init(void)
|
||||
+{
|
||||
+ /* By default, enable all L2 cache ways */
|
||||
+ int l2c_way = (readl((volatile void *)(FU540_CCACHE_CONTROLLER_ADDR +
|
||||
+ FU540_CCACHE_CONFIG_REG_OFF)) & FU540_CCR_WAY_MASK) >>
|
||||
+ FU540_CCR_WAY_BIT_OFF;
|
||||
+#ifdef FU540_CCACHE_ENABLEWAY_NUM
|
||||
+ if (FU540_CCACHE_ENABLEWAY_NUM < l2c_way)
|
||||
+ l2c_way = FU540_CCACHE_ENABLEWAY_NUM;
|
||||
+#endif
|
||||
+ writeb((char)l2c_way,
|
||||
+ (void *)(FU540_CCACHE_CONTROLLER_ADDR + FU540_CCACHE_WAYENABLE_REG_OFF));
|
||||
+}
|
||||
+
|
||||
static int fu540_final_init(bool cold_boot)
|
||||
{
|
||||
void *fdt;
|
||||
@@ -95,6 +116,7 @@ static int fu540_final_init(bool cold_boot)
|
||||
if (!cold_boot)
|
||||
return 0;
|
||||
|
||||
+ fu540_ccache_init();
|
||||
fdt = sbi_scratch_thishart_arg1_ptr();
|
||||
fu540_modify_dt(fdt);
|
||||
|
||||
--
|
||||
2.7.4
|
||||
|
||||
|
||||
_______________________________________________
|
||||
opensbi mailing list
|
||||
opensbi@lists.infradead.org
|
||||
http://lists.infradead.org/mailman/listinfo/opensbi
|
Loading…
Reference in New Issue
Block a user