Remove L2 patch (this will be done in FSBL)
The patch was posted to enable full L2 within FSBL. Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
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@ -16,7 +16,6 @@ URL: https://github.com/riscv/opensbi
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%global full_commit 813f7f4c250af9f7c9546f64778e9b35bb7d7dcb
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Source0: https://github.com/riscv/opensbi/archive/%{full_commit}.tar.gz
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Patch0: platform-enable-all-l2-cache-ways-for-sifive-fu540-by-default-v2.patch
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Patch1: 0001-Revert-lib-Remove-date-and-time-from-init-message.patch
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BuildRequires: systemd-udev
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Mon, 04 Nov 2019 22:46:17 -0800 (PST)
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From: Vincent Chen <vincent.chen@sifive.com>
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To: opensbi@lists.infradead.org
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Subject: [PATCH v2] platform: Enable all L2 cache ways for sifive fu540 by
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default
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Date: Tue, 5 Nov 2019 14:46:01 +0800
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Some bootloaders don't enable the entire cache on boot. To avoid
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performance degradation, the entire L2 cache should be enabled by
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default. If needed, the user can specify the enabled cache
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way number via the macro FU540_CCACHE_ENABLEWAY_NUM.
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Chnages from v1->v2
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1. Corrected the typo in the macro FU540_CCR_WAY_MASK definition
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2. Added/Removed empty line.
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Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
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---
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docs/platform/sifive_fu540.md | 18 ++++++++++++++++++
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platform/sifive/fu540/objects.mk | 3 +++
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platform/sifive/fu540/platform.c | 22 ++++++++++++++++++++++
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3 files changed, 43 insertions(+)
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diff --git a/docs/platform/sifive_fu540.md b/docs/platform/sifive_fu540.md
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index 9fb45d6..63f0b94 100644
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--- a/docs/platform/sifive_fu540.md
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+++ b/docs/platform/sifive_fu540.md
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@@ -13,6 +13,7 @@ To build platform specific library and firmwares, provide the
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Platform Options
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----------------
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+1. *FU540_ENABLED_HART_MASK*
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As hart0 in the FU540 doesn't have an MMU, only harts 1-4 boot by default.
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A hart mask i.e. *FU540_ENABLED_HART_MASK* compile time option is provided
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to select any other hart for booting. Please keep in mind that this is not
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@@ -24,6 +25,23 @@ make PLATFORM=sifive/fu540 FW_PAYLOAD_PATH=Image FU540_ENABLED_HART_MASK=0x02
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```
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This will let the board boot only hart1 instead of default 1-4.
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+2. *FU540_CCACHE_ENABLEWAY_NUM*
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+FU540 L2 cache controller offers extensive flexibility as it allows for several
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+features in addition to the L2 Cache functionality, such as memory-mapped
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+access to L2 Cache RAM for disabled cache ways and scratchpad functionality.
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+Out of reset, all ways, except for way 0, are disabled. Cache ways can be
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+enabled via the L2 controller register. By default, OpenSBI will enable all
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+cache ways. If needed, the enabled cache way number can be specified by the
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+following command:
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+
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+```
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+make PLATFORM=sifive/fu540 FW_PAYLOAD_PATH=Image FU540_CCACHE_ENABLEWAY_NUM=0x5
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+```
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+This will enable the way 1 through way 5. Please keep in mind that once a cache
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+way is enabled, it can not be disabled unless the FU540-C000 is reset. In other
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+words, the macro FU540_CCACHE_ENABLEWAY_NUM cannot disable the ways enabled by
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+FSBL or other bootloaders.
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+
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Building SiFive Fu540 Platform
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-----------------------------
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diff --git a/platform/sifive/fu540/objects.mk b/platform/sifive/fu540/objects.mk
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index f09a305..3f730ad 100644
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--- a/platform/sifive/fu540/objects.mk
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+++ b/platform/sifive/fu540/objects.mk
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@@ -11,3 +11,6 @@ platform-objs-y += platform.o
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ifdef FU540_ENABLED_HART_MASK
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platform-genflags-y += -DFU540_ENABLED_HART_MASK=$(FU540_ENABLED_HART_MASK)
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endif
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+ifdef FU540_CCACHE_ENABLEWAY_NUM
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+platform-genflags-y += -DFU540_CCACHE_ENABLEWAY_NUM=$(FU540_CCACHE_ENABLEWAY_NUM)
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+endif
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diff --git a/platform/sifive/fu540/platform.c b/platform/sifive/fu540/platform.c
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index 81e8e8d..974cc44 100644
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--- a/platform/sifive/fu540/platform.c
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+++ b/platform/sifive/fu540/platform.c
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@@ -36,6 +36,13 @@
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#define FU540_UART1_ADDR 0x10011000
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#define FU540_UART_BAUDRATE 115200
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+#define FU540_CCACHE_CONTROLLER_ADDR 0x02010000
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+#define FU540_CCACHE_CONFIG_REG_OFF 0x0
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+#define FU540_CCACHE_WAYENABLE_REG_OFF 0x8
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+
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+/* FU540 Cache Configuration Register */
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+#define FU540_CCR_WAY_BIT_OFF 0x8
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+#define FU540_CCR_WAY_MASK (0xff << FU540_CCR_WAY_BIT_OFF)
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/**
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* The FU540 SoC has 5 HARTs but HART ID 0 doesn't have S mode. enable only
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* HARTs 1 to 4.
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@@ -88,6 +95,20 @@ static void fu540_modify_dt(void *fdt)
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plic_fdt_fixup(fdt, "riscv,plic0");
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}
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+static void fu540_ccache_init(void)
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+{
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+ /* By default, enable all L2 cache ways */
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+ int l2c_way = (readl((volatile void *)(FU540_CCACHE_CONTROLLER_ADDR +
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+ FU540_CCACHE_CONFIG_REG_OFF)) & FU540_CCR_WAY_MASK) >>
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+ FU540_CCR_WAY_BIT_OFF;
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+#ifdef FU540_CCACHE_ENABLEWAY_NUM
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+ if (FU540_CCACHE_ENABLEWAY_NUM < l2c_way)
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+ l2c_way = FU540_CCACHE_ENABLEWAY_NUM;
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+#endif
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+ writeb((char)l2c_way,
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+ (void *)(FU540_CCACHE_CONTROLLER_ADDR + FU540_CCACHE_WAYENABLE_REG_OFF));
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+}
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+
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static int fu540_final_init(bool cold_boot)
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{
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void *fdt;
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@@ -95,6 +116,7 @@ static int fu540_final_init(bool cold_boot)
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if (!cold_boot)
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return 0;
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+ fu540_ccache_init();
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fdt = sbi_scratch_thishart_arg1_ptr();
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fu540_modify_dt(fdt);
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--
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2.7.4
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