kernel-ark/arch/ia64
Chen, Kenneth W fedb25fae7 [IA64] 4 level page table bug fix in vhpt_miss
From source code inspection, I think there is a bug with 4 level
page table with vhpt_miss handler.  In the code path of rechecking
page table entry against previously read value after tlb insertion,
*pte value in register r18 was overwritten with value newly read
from pud pointer, render the check of new *pte against previous
*pte completely wrong.  Though the bug is none fatal and the penalty
is to purge the entry and retry.  For functional correctness, it
should be fixed.  The fix is to use a different register so new
*pud don't trash *pte.  (btw, the comments in the cmp statement is
wrong as well, which I will address in the next patch).

Signed-off-by: Ken Chen <kenneth.w.chen@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
2005-11-17 09:47:18 -08:00
..
configs [IA64] 4-level page tables 2005-11-11 09:37:29 -08:00
dig
hp
ia32
kernel [IA64] 4 level page table bug fix in vhpt_miss 2005-11-17 09:47:18 -08:00
lib
mm Pull context-bitmap into release branch 2005-11-10 10:39:49 -08:00
oprofile
pci
scripts
sn [IA64-SGI] set altix preferred console 2005-11-11 11:24:26 -08:00
defconfig [IA64] 4-level page tables 2005-11-11 09:37:29 -08:00
install.sh
Kconfig Merge x86-64 update from Andi 2005-11-14 19:56:02 -08:00
Kconfig.debug
Makefile
module.lds