23bdf86aa0
Patch from Lennert Buytenhek This patch adds support for the new XScale v3 core. This is an ARMv5 ISA core with the following additions: - L2 cache - I/O coherency support (on select chipsets) - Low-Locality Reference cache attributes (replaces mini-cache) - Supersections (v6 compatible) - 36-bit addressing (v6 compatible) - Single instruction cache line clean/invalidate - LRU cache replacement (vs round-robin) I attempted to merge the XSC3 support into proc-xscale.S, but XSC3 cores have separate errata and have to handle things like L2, so it is simpler to keep it separate. L2 cache support is currently a build option because the L2 enable bit must be set before we enable the MMU and there is no easy way to capture command line parameters at this point. There are still optimizations that can be done such as using LLR for copypage (in theory using the exisiting mini-cache code) but those can be addressed down the road. Signed-off-by: Deepak Saxena <dsaxena@plexity.net> Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
71 lines
1.9 KiB
C
71 lines
1.9 KiB
C
/*
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* linux/include/asm-arm/domain.h
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*
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* Copyright (C) 1999 Russell King.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_PROC_DOMAIN_H
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#define __ASM_PROC_DOMAIN_H
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/*
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* Domain numbers
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*
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* DOMAIN_IO - domain 2 includes all IO only
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* DOMAIN_USER - domain 1 includes all user memory only
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* DOMAIN_KERNEL - domain 0 includes all kernel memory only
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*
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* The domain numbering depends on whether we support 36 physical
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* address for I/O or not. Addresses above the 32 bit boundary can
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* only be mapped using supersections and supersections can only
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* be set for domain 0. We could just default to DOMAIN_IO as zero,
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* but there may be systems with supersection support and no 36-bit
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* addressing. In such cases, we want to map system memory with
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* supersections to reduce TLB misses and footprint.
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*
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* 36-bit addressing and supersections are only available on
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* CPUs based on ARMv6+ or the Intel XSC3 core.
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*/
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#ifndef CONFIG_IO_36
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#define DOMAIN_KERNEL 0
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#define DOMAIN_TABLE 0
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#define DOMAIN_USER 1
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#define DOMAIN_IO 2
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#else
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#define DOMAIN_KERNEL 2
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#define DOMAIN_TABLE 2
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#define DOMAIN_USER 1
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#define DOMAIN_IO 0
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#endif
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/*
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* Domain types
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*/
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#define DOMAIN_NOACCESS 0
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#define DOMAIN_CLIENT 1
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#define DOMAIN_MANAGER 3
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#define domain_val(dom,type) ((type) << (2*(dom)))
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#ifndef __ASSEMBLY__
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#define set_domain(x) \
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do { \
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__asm__ __volatile__( \
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"mcr p15, 0, %0, c3, c0 @ set domain" \
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: : "r" (x)); \
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} while (0)
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#define modify_domain(dom,type) \
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do { \
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struct thread_info *thread = current_thread_info(); \
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unsigned int domain = thread->cpu_domain; \
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domain &= ~domain_val(dom, DOMAIN_MANAGER); \
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thread->cpu_domain = domain | domain_val(dom, type); \
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set_domain(thread->cpu_domain); \
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} while (0)
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#endif
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#endif /* !__ASSEMBLY__ */
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