f79abb627f
The DMA_INTERRUPT async_tx is a NULL transfer, thus the BCR(count register) is 0. When the transfer started with a byte count of zero, the DMA controller will triger a PE(programming error) event and halt, not a normal interrupt. I add special codes for PE event and DMA_INTERRUPT async_tx testing. Signed-off-by: Zhang Wei <wei.zhang@freescale.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Dan Williams <dan.j.williams@intel.com> |
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| .. | ||
| dmaengine.c | ||
| fsldma.c | ||
| fsldma.h | ||
| ioat_dca.c | ||
| ioat_dma.c | ||
| ioat.c | ||
| ioatdma_hw.h | ||
| ioatdma_registers.h | ||
| ioatdma.h | ||
| iop-adma.c | ||
| iovlock.c | ||
| Kconfig | ||
| Makefile | ||