5f53d8ca3d
Driver from Realtek for the Realtek RTL8192 USB wifi device Based on the r8187 driver from Andrea Merello <andreamrl@tiscali.it> and others. Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
293 lines
7.5 KiB
C
293 lines
7.5 KiB
C
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#include "r8192U.h"
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#include "r8192S_hw.h"
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#include "r8192S_phyreg.h"
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#include "r8192S_phy.h"
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#include "r8192S_rtl8225.h"
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/*---------------------Define local function prototype-----------------------*/
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void phy_RF8225_Config_HardCode(struct net_device* dev );
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bool phy_RF8225_Config_ParaFile(struct net_device* dev );
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/*---------------------Define local function prototype-----------------------*/
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void PHY_SetRF8225OfdmTxPower(struct net_device* dev ,u8 powerlevel)
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{
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}
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void PHY_SetRF8225CckTxPower( struct net_device* dev , u8 powerlevel)
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{
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}
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// TODO: The following RF 022D related function should be removed to HalPhy0222D.c.
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void PHY_SetRF0222DOfdmTxPower(struct net_device* dev ,u8 powerlevel)
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{
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//TODO: We should set RF TxPower for RF 0222D here!!
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}
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void PHY_SetRF0222DCckTxPower(struct net_device* dev ,u8 powerlevel)
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{
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//TODO: We should set RF TxPower for RF 0222D here!!
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}
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/*-----------------------------------------------------------------------------
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* Function: PHY_SetRF0222DBandwidth()
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*
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* Overview: This function is called by SetBWModeCallback8190Pci() only
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*
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* Input: PADAPTER Adapter
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* WIRELESS_BANDWIDTH_E Bandwidth //20M or 40M
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*
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* Output: NONE
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*
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* Return: NONE
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*
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* Note: For RF type 0222D
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*---------------------------------------------------------------------------*/
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//just in phy
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void PHY_SetRF0222DBandwidth(struct net_device* dev , HT_CHANNEL_WIDTH Bandwidth) //20M or 40M
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{
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u8 eRFPath;
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struct r8192_priv *priv = ieee80211_priv(dev);
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//if (IS_HARDWARE_TYPE_8192S(dev))
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if (1)
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{
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#ifndef RTL92SE_FPGA_VERIFY
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switch(Bandwidth)
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{
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case HT_CHANNEL_WIDTH_20:
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#ifdef FIB_MODIFICATION
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write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x58);
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#endif
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rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, BIT10|BIT11, 0x01);
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break;
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case HT_CHANNEL_WIDTH_20_40:
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#ifdef FIB_MODIFICATION
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write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x18);
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#endif
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rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, BIT10|BIT11, 0x00);
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break;
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default:
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;//RT_TRACE(COMP_DBG, DBG_LOUD, ("PHY_SetRF8225Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth ));
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break;
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}
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#endif
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}
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else
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{
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for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
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{
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switch(Bandwidth)
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{
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case HT_CHANNEL_WIDTH_20:
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//rtl8192_phy_SetRFReg(Adapter, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, (BIT10|BIT11), 0x01);
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break;
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case HT_CHANNEL_WIDTH_20_40:
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//rtl8192_phy_SetRFReg(Adapter, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, (BIT10|BIT11), 0x00);
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break;
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default:
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;//RT_TRACE(COMP_DBG, DBG_LOUD, ("PHY_SetRF8225Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth ));
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break;
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}
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}
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}
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}
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// TODO: Aabove RF 022D related function should be removed to HalPhy0222D.c.
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/*-----------------------------------------------------------------------------
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* Function: PHY_SetRF8225Bandwidth()
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*
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* Overview: This function is called by SetBWModeCallback8190Pci() only
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*
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* Input: PADAPTER Adapter
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* WIRELESS_BANDWIDTH_E Bandwidth //20M or 40M
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*
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* Output: NONE
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*
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* Return: NONE
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*
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* Note: 8225(zebra1) support 20M only
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*---------------------------------------------------------------------------*/
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//just in phy
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void PHY_SetRF8225Bandwidth(struct net_device* dev ,HT_CHANNEL_WIDTH Bandwidth) //20M or 40M
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{
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u8 eRFPath;
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struct r8192_priv *priv = ieee80211_priv(dev);
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//for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
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for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
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{
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switch(Bandwidth)
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{
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case HT_CHANNEL_WIDTH_20:
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// TODO: Update the parameters here
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break;
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case HT_CHANNEL_WIDTH_20_40:
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RT_TRACE(COMP_DBG, "SetChannelBandwidth8190Pci():8225 does not support 40M mode\n");
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break;
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default:
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RT_TRACE(COMP_DBG, "PHY_SetRF8225Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth );
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break;
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}
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}
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}
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//just in phy
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bool PHY_RF8225_Config(struct net_device* dev )
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{
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struct r8192_priv *priv = ieee80211_priv(dev);
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bool rtStatus = true;
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//RF90_RADIO_PATH_E eRFPath;
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//BB_REGISTER_DEFINITION_T *pPhyReg;
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//u32 OrgStoreRFIntSW[RF90_PATH_D+1];
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//
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// Initialize general global value
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//
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// TODO: Extend RF_PATH_C and RF_PATH_D in the future
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priv->NumTotalRFPath = 2;
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//
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// Config BB and RF
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//
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//switch( Adapter->MgntInfo.bRegHwParaFile )
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//{
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// case 0:
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// phy_RF8225_Config_HardCode(dev);
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// break;
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// case 1:
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// rtStatus = phy_RF8225_Config_ParaFile(dev);
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// break;
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// case 2:
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// Partial Modify.
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phy_RF8225_Config_HardCode(dev);
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phy_RF8225_Config_ParaFile(dev);
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// break;
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// default:
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// phy_RF8225_Config_HardCode(dev);
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// break;
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//}
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return rtStatus;
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}
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//just in 8225
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void phy_RF8225_Config_HardCode(struct net_device* dev)
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{
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// Set Default Bandwidth to 20M
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//Adapter->HalFunc .SetBWModeHandler(Adapter, HT_CHANNEL_WIDTH_20);
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// TODO: Set Default Channel to channel one for RTL8225
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}
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//just in 8225
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bool phy_RF8225_Config_ParaFile(struct net_device* dev)
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{
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u32 u4RegValue = 0;
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//static char szRadioAFile[] = RTL819X_PHY_RADIO_A;
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//static char szRadioBFile[] = RTL819X_PHY_RADIO_B;
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u8 eRFPath;
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bool rtStatus = true;
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struct r8192_priv *priv = ieee80211_priv(dev);
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BB_REGISTER_DEFINITION_T *pPhyReg;
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//u8 eCheckItem;
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#if 1
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//3//-----------------------------------------------------------------
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//3// <2> Initialize RF
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//3//-----------------------------------------------------------------
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//for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
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for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
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{
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pPhyReg = &priv->PHYRegDef[eRFPath];
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/*----Store original RFENV control type----*/
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switch(eRFPath)
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{
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case RF90_PATH_A:
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case RF90_PATH_C:
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u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV);
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break;
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case RF90_PATH_B :
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case RF90_PATH_D:
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u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16);
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break;
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}
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/*----Set RF_ENV enable----*/
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rtl8192_setBBreg(dev, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1);
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/*----Set RF_ENV output high----*/
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rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
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/* Set bit number of Address and Data for RF register */
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rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); // Set 1 to 4 bits for 8255
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rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); // Set 0 to 12 bits for 8255
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/*----Initialize RF fom connfiguration file----*/
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switch(eRFPath)
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{
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case RF90_PATH_A:
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//rtStatus = PHY_ConfigRFWithParaFile(dev, (char* )&szRadioAFile, (RF90_RADIO_PATH_E)eRFPath);
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rtStatus = rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath);
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break;
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case RF90_PATH_B:
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//rtStatus = PHY_ConfigRFWithParaFile(dev, (char* )&szRadioBFile, (RF90_RADIO_PATH_E)eRFPath);
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rtStatus = rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath);
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break;
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case RF90_PATH_C:
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break;
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case RF90_PATH_D:
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break;
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}
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/*----Restore RFENV control type----*/;
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switch(eRFPath)
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{
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case RF90_PATH_A:
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case RF90_PATH_C:
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rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue);
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break;
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case RF90_PATH_B :
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case RF90_PATH_D:
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rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue);
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break;
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}
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if(rtStatus == false){
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//RT_TRACE(COMP_FPGA, DBG_LOUD, ("phy_RF8225_Config_ParaFile():Radio[%d] Fail!!", eRFPath));
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goto phy_RF8225_Config_ParaFile_Fail;
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}
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}
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//RT_TRACE(COMP_INIT, DBG_LOUD, ("<---phy_RF8225_Config_ParaFile()\n"));
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return rtStatus;
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phy_RF8225_Config_ParaFile_Fail:
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#endif
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return rtStatus;
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}
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