f6c2e3330d
We should zap the low mappings, as soon as possible, so that we can catch kernel bugs more effectively. Previously early boot had NULL mapped and didn't trap on NULL references. This patch introduces boot_level4_pgt, which will always have low identity addresses mapped. Druing boot, all the processors will use this as their level4 pgt. On BP, we will switch to init_level4_pgt as soon as we enter C code and zap the low mappings as soon as we are done with the usage of identity low mapped addresses. On AP's we will zap the low mappings as soon as we jump to C code. Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Signed-off-by: Ashok Raj <ashok.raj@intel.com> Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
139 lines
3.0 KiB
C
139 lines
3.0 KiB
C
#ifndef __ASM_SMP_H
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#define __ASM_SMP_H
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/*
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* We need the APIC definitions automatically as part of 'smp.h'
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*/
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#ifndef __ASSEMBLY__
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#include <linux/config.h>
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#include <linux/threads.h>
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#include <linux/cpumask.h>
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#include <linux/bitops.h>
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extern int disable_apic;
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#endif
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#ifdef CONFIG_X86_LOCAL_APIC
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#ifndef __ASSEMBLY__
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#include <asm/fixmap.h>
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#include <asm/mpspec.h>
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#ifdef CONFIG_X86_IO_APIC
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#include <asm/io_apic.h>
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#endif
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#include <asm/apic.h>
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#include <asm/thread_info.h>
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#endif
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#endif
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#ifdef CONFIG_SMP
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#ifndef ASSEMBLY
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#include <asm/pda.h>
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struct pt_regs;
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extern cpumask_t cpu_present_mask;
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extern cpumask_t cpu_possible_map;
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extern cpumask_t cpu_online_map;
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extern cpumask_t cpu_callout_map;
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/*
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* Private routines/data
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*/
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extern void smp_alloc_memory(void);
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extern volatile unsigned long smp_invalidate_needed;
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extern int pic_mode;
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extern void lock_ipi_call_lock(void);
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extern void unlock_ipi_call_lock(void);
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extern int smp_num_siblings;
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extern void smp_send_reschedule(int cpu);
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void smp_stop_cpu(void);
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extern int smp_call_function_single(int cpuid, void (*func) (void *info),
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void *info, int retry, int wait);
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extern cpumask_t cpu_sibling_map[NR_CPUS];
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extern cpumask_t cpu_core_map[NR_CPUS];
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extern u8 phys_proc_id[NR_CPUS];
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extern u8 cpu_core_id[NR_CPUS];
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#define SMP_TRAMPOLINE_BASE 0x6000
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/*
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* On x86 all CPUs are mapped 1:1 to the APIC space.
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* This simplifies scheduling and IPI sending and
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* compresses data structures.
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*/
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static inline int num_booting_cpus(void)
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{
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return cpus_weight(cpu_callout_map);
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}
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#define raw_smp_processor_id() read_pda(cpunumber)
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static inline int hard_smp_processor_id(void)
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{
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/* we don't want to mark this access volatile - bad code generation */
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return GET_APIC_ID(*(unsigned int *)(APIC_BASE+APIC_ID));
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}
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extern int safe_smp_processor_id(void);
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extern int __cpu_disable(void);
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extern void __cpu_die(unsigned int cpu);
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extern void prefill_possible_map(void);
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#endif /* !ASSEMBLY */
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#define NO_PROC_ID 0xFF /* No processor magic marker */
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#endif
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#ifndef ASSEMBLY
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/*
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* Some lowlevel functions might want to know about
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* the real APIC ID <-> CPU # mapping.
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*/
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extern u8 x86_cpu_to_apicid[NR_CPUS]; /* physical ID */
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extern u8 x86_cpu_to_log_apicid[NR_CPUS];
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extern u8 bios_cpu_apicid[];
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static inline unsigned int cpu_mask_to_apicid(cpumask_t cpumask)
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{
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return cpus_addr(cpumask)[0];
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}
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static inline int cpu_present_to_apicid(int mps_cpu)
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{
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if (mps_cpu < NR_CPUS)
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return (int)bios_cpu_apicid[mps_cpu];
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else
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return BAD_APICID;
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}
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#endif /* !ASSEMBLY */
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#ifndef CONFIG_SMP
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#define stack_smp_processor_id() 0
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#define safe_smp_processor_id() 0
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#define cpu_logical_map(x) (x)
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#else
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#include <asm/thread_info.h>
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#define stack_smp_processor_id() \
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({ \
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struct thread_info *ti; \
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__asm__("andq %%rsp,%0; ":"=r" (ti) : "0" (CURRENT_MASK)); \
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ti->cpu; \
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})
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#endif
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#ifndef __ASSEMBLY__
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static __inline int logical_smp_processor_id(void)
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{
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/* we don't want to mark this access volatile - bad code generation */
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return GET_APIC_LOGICAL_ID(*(unsigned long *)(APIC_BASE+APIC_LDR));
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}
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#endif
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#endif
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