f637ef8ea0
DIU platform code should not just write to the PIXIS' BRDCFG0 register, it should set and clear its own bits only, otherwise it will break firmware setup (in fact it breaks second uart). Also get rid of magic numbers in the related code. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
415 lines
11 KiB
C
415 lines
11 KiB
C
/*
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* MPC8610 HPCD board specific routines
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*
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* Initial author: Xianghua Xiao <x.xiao@freescale.com>
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* Recode: Jason Jin <jason.jin@freescale.com>
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* York Sun <yorksun@freescale.com>
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*
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* Rewrite the interrupt routing. remove the 8259PIC support,
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* All the integrated device in ULI use sideband interrupt.
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*
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* Copyright 2008 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/kdev_t.h>
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#include <linux/delay.h>
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#include <linux/seq_file.h>
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#include <linux/of.h>
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#include <asm/system.h>
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#include <asm/time.h>
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#include <asm/machdep.h>
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#include <asm/pci-bridge.h>
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#include <asm/mpc86xx.h>
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#include <asm/prom.h>
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#include <mm/mmu_decl.h>
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#include <asm/udbg.h>
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#include <asm/mpic.h>
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#include <linux/of_platform.h>
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#include <sysdev/fsl_pci.h>
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#include <sysdev/fsl_soc.h>
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static unsigned char *pixis_bdcfg0, *pixis_arch;
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static struct of_device_id __initdata mpc8610_ids[] = {
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{ .compatible = "fsl,mpc8610-immr", },
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{ .compatible = "simple-bus", },
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{}
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};
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static int __init mpc8610_declare_of_platform_devices(void)
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{
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/* Without this call, the SSI device driver won't get probed. */
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of_platform_bus_probe(NULL, mpc8610_ids, NULL);
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return 0;
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}
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machine_device_initcall(mpc86xx_hpcd, mpc8610_declare_of_platform_devices);
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static void __init mpc86xx_hpcd_init_irq(void)
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{
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struct mpic *mpic1;
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struct device_node *np;
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struct resource res;
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/* Determine PIC address. */
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np = of_find_node_by_type(NULL, "open-pic");
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if (np == NULL)
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return;
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of_address_to_resource(np, 0, &res);
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/* Alloc mpic structure and per isu has 16 INT entries. */
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mpic1 = mpic_alloc(np, res.start,
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MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
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0, 256, " MPIC ");
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BUG_ON(mpic1 == NULL);
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mpic_init(mpic1);
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}
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#ifdef CONFIG_PCI
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static void __devinit quirk_uli1575(struct pci_dev *dev)
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{
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u32 temp32;
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/* Disable INTx */
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pci_read_config_dword(dev, 0x48, &temp32);
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pci_write_config_dword(dev, 0x48, (temp32 | 1<<26));
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/* Enable sideband interrupt */
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pci_read_config_dword(dev, 0x90, &temp32);
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pci_write_config_dword(dev, 0x90, (temp32 | 1<<22));
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}
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static void __devinit quirk_uli5288(struct pci_dev *dev)
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{
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unsigned char c;
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unsigned short temp;
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/* Interrupt Disable, Needed when SATA disabled */
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pci_read_config_word(dev, PCI_COMMAND, &temp);
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temp |= 1<<10;
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pci_write_config_word(dev, PCI_COMMAND, temp);
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pci_read_config_byte(dev, 0x83, &c);
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c |= 0x80;
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pci_write_config_byte(dev, 0x83, c);
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pci_write_config_byte(dev, PCI_CLASS_PROG, 0x01);
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pci_write_config_byte(dev, PCI_CLASS_DEVICE, 0x06);
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pci_read_config_byte(dev, 0x83, &c);
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c &= 0x7f;
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pci_write_config_byte(dev, 0x83, c);
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}
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/*
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* Since 8259PIC was disabled on the board, the IDE device can not
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* use the legacy IRQ, we need to let the IDE device work under
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* native mode and use the interrupt line like other PCI devices.
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* IRQ14 is a sideband interrupt from IDE device to CPU and we use this
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* as the interrupt for IDE device.
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*/
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static void __devinit quirk_uli5229(struct pci_dev *dev)
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{
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unsigned char c;
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pci_read_config_byte(dev, 0x4b, &c);
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c |= 0x10;
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pci_write_config_byte(dev, 0x4b, c);
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}
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/*
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* SATA interrupt pin bug fix
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* There's a chip bug for 5288, The interrupt pin should be 2,
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* not the read only value 1, So it use INTB#, not INTA# which
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* actually used by the IDE device 5229.
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* As of this bug, during the PCI initialization, 5288 read the
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* irq of IDE device from the device tree, this function fix this
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* bug by re-assigning a correct irq to 5288.
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*
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*/
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static void __devinit final_uli5288(struct pci_dev *dev)
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{
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struct pci_controller *hose = pci_bus_to_host(dev->bus);
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struct device_node *hosenode = hose ? hose->dn : NULL;
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struct of_irq oirq;
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int virq, pin = 2;
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u32 laddr[3];
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if (!hosenode)
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return;
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laddr[0] = (hose->first_busno << 16) | (PCI_DEVFN(31, 0) << 8);
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laddr[1] = laddr[2] = 0;
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of_irq_map_raw(hosenode, &pin, 1, laddr, &oirq);
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virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
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oirq.size);
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dev->irq = virq;
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575, quirk_uli1575);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5288, quirk_uli5288);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, 0x5288, final_uli5288);
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#endif /* CONFIG_PCI */
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#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
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static u32 get_busfreq(void)
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{
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struct device_node *node;
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u32 fs_busfreq = 0;
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node = of_find_node_by_type(NULL, "cpu");
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if (node) {
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unsigned int size;
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const unsigned int *prop =
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of_get_property(node, "bus-frequency", &size);
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if (prop)
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fs_busfreq = *prop;
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of_node_put(node);
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};
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return fs_busfreq;
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}
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unsigned int mpc8610hpcd_get_pixel_format(unsigned int bits_per_pixel,
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int monitor_port)
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{
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static const unsigned long pixelformat[][3] = {
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{0x88882317, 0x88083218, 0x65052119},
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{0x88883316, 0x88082219, 0x65053118},
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};
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unsigned int pix_fmt, arch_monitor;
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arch_monitor = ((*pixis_arch == 0x01) && (monitor_port == 0))? 0 : 1;
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/* DVI port for board version 0x01 */
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if (bits_per_pixel == 32)
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pix_fmt = pixelformat[arch_monitor][0];
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else if (bits_per_pixel == 24)
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pix_fmt = pixelformat[arch_monitor][1];
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else if (bits_per_pixel == 16)
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pix_fmt = pixelformat[arch_monitor][2];
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else
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pix_fmt = pixelformat[1][0];
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return pix_fmt;
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}
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void mpc8610hpcd_set_gamma_table(int monitor_port, char *gamma_table_base)
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{
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int i;
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if (monitor_port == 2) { /* dual link LVDS */
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for (i = 0; i < 256*3; i++)
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gamma_table_base[i] = (gamma_table_base[i] << 2) |
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((gamma_table_base[i] >> 6) & 0x03);
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}
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}
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#define PX_BRDCFG0_DVISEL (1 << 3)
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#define PX_BRDCFG0_DLINK (1 << 4)
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#define PX_BRDCFG0_DIU_MASK (PX_BRDCFG0_DVISEL | PX_BRDCFG0_DLINK)
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void mpc8610hpcd_set_monitor_port(int monitor_port)
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{
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static const u8 bdcfg[] = {
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PX_BRDCFG0_DVISEL | PX_BRDCFG0_DLINK,
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PX_BRDCFG0_DLINK,
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0,
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};
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if (monitor_port < 3)
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clrsetbits_8(pixis_bdcfg0, PX_BRDCFG0_DIU_MASK,
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bdcfg[monitor_port]);
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}
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void mpc8610hpcd_set_pixel_clock(unsigned int pixclock)
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{
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u32 __iomem *clkdvdr;
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u32 temp;
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/* variables for pixel clock calcs */
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ulong bestval, bestfreq, speed_ccb, minpixclock, maxpixclock;
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ulong pixval;
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long err;
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int i;
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clkdvdr = ioremap(get_immrbase() + 0xe0800, sizeof(u32));
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if (!clkdvdr) {
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printk(KERN_ERR "Err: can't map clock divider register!\n");
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return;
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}
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/* Pixel Clock configuration */
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pr_debug("DIU: Bus Frequency = %d\n", get_busfreq());
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speed_ccb = get_busfreq();
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/* Calculate the pixel clock with the smallest error */
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/* calculate the following in steps to avoid overflow */
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pr_debug("DIU pixclock in ps - %d\n", pixclock);
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temp = 1000000000/pixclock;
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temp *= 1000;
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pixclock = temp;
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pr_debug("DIU pixclock freq - %u\n", pixclock);
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temp = pixclock * 5 / 100;
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pr_debug("deviation = %d\n", temp);
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minpixclock = pixclock - temp;
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maxpixclock = pixclock + temp;
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pr_debug("DIU minpixclock - %lu\n", minpixclock);
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pr_debug("DIU maxpixclock - %lu\n", maxpixclock);
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pixval = speed_ccb/pixclock;
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pr_debug("DIU pixval = %lu\n", pixval);
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err = 100000000;
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bestval = pixval;
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pr_debug("DIU bestval = %lu\n", bestval);
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bestfreq = 0;
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for (i = -1; i <= 1; i++) {
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temp = speed_ccb / ((pixval+i) + 1);
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pr_debug("DIU test pixval i= %d, pixval=%lu, temp freq. = %u\n",
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i, pixval, temp);
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if ((temp < minpixclock) || (temp > maxpixclock))
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pr_debug("DIU exceeds monitor range (%lu to %lu)\n",
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minpixclock, maxpixclock);
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else if (abs(temp - pixclock) < err) {
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pr_debug("Entered the else if block %d\n", i);
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err = abs(temp - pixclock);
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bestval = pixval+i;
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bestfreq = temp;
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}
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}
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pr_debug("DIU chose = %lx\n", bestval);
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pr_debug("DIU error = %ld\n NomPixClk ", err);
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pr_debug("DIU: Best Freq = %lx\n", bestfreq);
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/* Modify PXCLK in GUTS CLKDVDR */
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pr_debug("DIU: Current value of CLKDVDR = 0x%08x\n", (*clkdvdr));
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temp = (*clkdvdr) & 0x2000FFFF;
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*clkdvdr = temp; /* turn off clock */
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*clkdvdr = temp | 0x80000000 | (((bestval) & 0x1F) << 16);
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pr_debug("DIU: Modified value of CLKDVDR = 0x%08x\n", (*clkdvdr));
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iounmap(clkdvdr);
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}
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ssize_t mpc8610hpcd_show_monitor_port(int monitor_port, char *buf)
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{
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return snprintf(buf, PAGE_SIZE,
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"%c0 - DVI\n"
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"%c1 - Single link LVDS\n"
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"%c2 - Dual link LVDS\n",
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monitor_port == 0 ? '*' : ' ',
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monitor_port == 1 ? '*' : ' ',
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monitor_port == 2 ? '*' : ' ');
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}
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int mpc8610hpcd_set_sysfs_monitor_port(int val)
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{
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return val < 3 ? val : 0;
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}
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#endif
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static void __init mpc86xx_hpcd_setup_arch(void)
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{
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struct resource r;
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struct device_node *np;
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unsigned char *pixis;
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if (ppc_md.progress)
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ppc_md.progress("mpc86xx_hpcd_setup_arch()", 0);
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#ifdef CONFIG_PCI
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for_each_node_by_type(np, "pci") {
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if (of_device_is_compatible(np, "fsl,mpc8610-pci")
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|| of_device_is_compatible(np, "fsl,mpc8641-pcie")) {
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struct resource rsrc;
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of_address_to_resource(np, 0, &rsrc);
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if ((rsrc.start & 0xfffff) == 0xa000)
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fsl_add_bridge(np, 1);
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else
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fsl_add_bridge(np, 0);
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}
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}
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#endif
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#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
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preallocate_diu_videomemory();
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diu_ops.get_pixel_format = mpc8610hpcd_get_pixel_format;
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diu_ops.set_gamma_table = mpc8610hpcd_set_gamma_table;
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diu_ops.set_monitor_port = mpc8610hpcd_set_monitor_port;
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diu_ops.set_pixel_clock = mpc8610hpcd_set_pixel_clock;
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diu_ops.show_monitor_port = mpc8610hpcd_show_monitor_port;
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diu_ops.set_sysfs_monitor_port = mpc8610hpcd_set_sysfs_monitor_port;
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#endif
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np = of_find_compatible_node(NULL, NULL, "fsl,fpga-pixis");
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if (np) {
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of_address_to_resource(np, 0, &r);
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of_node_put(np);
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pixis = ioremap(r.start, 32);
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if (!pixis) {
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printk(KERN_ERR "Err: can't map FPGA cfg register!\n");
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return;
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}
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pixis_bdcfg0 = pixis + 8;
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pixis_arch = pixis + 1;
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} else
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printk(KERN_ERR "Err: "
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"can't find device node 'fsl,fpga-pixis'\n");
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printk("MPC86xx HPCD board from Freescale Semiconductor\n");
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}
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/*
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* Called very early, device-tree isn't unflattened
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*/
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static int __init mpc86xx_hpcd_probe(void)
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{
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unsigned long root = of_get_flat_dt_root();
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if (of_flat_dt_is_compatible(root, "fsl,MPC8610HPCD"))
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return 1; /* Looks good */
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return 0;
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}
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static long __init mpc86xx_time_init(void)
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{
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unsigned int temp;
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/* Set the time base to zero */
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mtspr(SPRN_TBWL, 0);
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mtspr(SPRN_TBWU, 0);
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temp = mfspr(SPRN_HID0);
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temp |= HID0_TBEN;
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mtspr(SPRN_HID0, temp);
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asm volatile("isync");
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return 0;
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}
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define_machine(mpc86xx_hpcd) {
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.name = "MPC86xx HPCD",
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.probe = mpc86xx_hpcd_probe,
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.setup_arch = mpc86xx_hpcd_setup_arch,
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.init_IRQ = mpc86xx_hpcd_init_irq,
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.get_irq = mpic_get_irq,
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.restart = fsl_rstcr_restart,
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.time_init = mpc86xx_time_init,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
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};
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