4267ea72bb
On an arch 2.06 hypervisor, a pending perfmon interrupt will be delivered to the hypervisor at any point the guest is running, regardless of MSR[EE]. In order to reflect this interrupt, the hypervisor has to mask the interrupt in PMGC0 -- and set MSRP[PMMP] to intercept futher guest accesses to the PMRs to detect when to unmask (and prevent the guest from unmasking early, or seeing inconsistent state). This has the side effect of ignoring any changes the guest makes to MSR[PMM], so wait until after the interrupt is clear, and thus the hypervisor should have cleared MSRP[PMMP], before setting MSR[PMM]. The counters wil not actually run until PMGC0[FAC] is cleared in pmc_start_ctrs(), so this will not reduce the effectiveness of PMM. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
357 lines
6.5 KiB
C
357 lines
6.5 KiB
C
/*
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* Freescale Embedded oprofile support, based on ppc64 oprofile support
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* Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM
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*
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* Copyright (c) 2004, 2010 Freescale Semiconductor, Inc
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*
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* Author: Andy Fleming
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* Maintainer: Kumar Gala <galak@kernel.crashing.org>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/oprofile.h>
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <asm/ptrace.h>
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#include <asm/system.h>
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#include <asm/processor.h>
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#include <asm/cputable.h>
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#include <asm/reg_fsl_emb.h>
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#include <asm/page.h>
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#include <asm/pmc.h>
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#include <asm/oprofile_impl.h>
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static unsigned long reset_value[OP_MAX_COUNTER];
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static int num_counters;
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static int oprofile_running;
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static inline u32 get_pmlca(int ctr)
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{
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u32 pmlca;
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switch (ctr) {
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case 0:
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pmlca = mfpmr(PMRN_PMLCA0);
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break;
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case 1:
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pmlca = mfpmr(PMRN_PMLCA1);
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break;
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case 2:
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pmlca = mfpmr(PMRN_PMLCA2);
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break;
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case 3:
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pmlca = mfpmr(PMRN_PMLCA3);
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break;
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default:
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panic("Bad ctr number\n");
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}
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return pmlca;
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}
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static inline void set_pmlca(int ctr, u32 pmlca)
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{
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switch (ctr) {
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case 0:
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mtpmr(PMRN_PMLCA0, pmlca);
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break;
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case 1:
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mtpmr(PMRN_PMLCA1, pmlca);
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break;
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case 2:
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mtpmr(PMRN_PMLCA2, pmlca);
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break;
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case 3:
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mtpmr(PMRN_PMLCA3, pmlca);
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break;
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default:
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panic("Bad ctr number\n");
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}
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}
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static inline unsigned int ctr_read(unsigned int i)
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{
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switch(i) {
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case 0:
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return mfpmr(PMRN_PMC0);
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case 1:
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return mfpmr(PMRN_PMC1);
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case 2:
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return mfpmr(PMRN_PMC2);
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case 3:
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return mfpmr(PMRN_PMC3);
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default:
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return 0;
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}
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}
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static inline void ctr_write(unsigned int i, unsigned int val)
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{
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switch(i) {
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case 0:
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mtpmr(PMRN_PMC0, val);
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break;
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case 1:
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mtpmr(PMRN_PMC1, val);
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break;
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case 2:
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mtpmr(PMRN_PMC2, val);
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break;
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case 3:
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mtpmr(PMRN_PMC3, val);
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break;
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default:
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break;
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}
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}
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static void init_pmc_stop(int ctr)
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{
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u32 pmlca = (PMLCA_FC | PMLCA_FCS | PMLCA_FCU |
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PMLCA_FCM1 | PMLCA_FCM0);
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u32 pmlcb = 0;
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switch (ctr) {
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case 0:
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mtpmr(PMRN_PMLCA0, pmlca);
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mtpmr(PMRN_PMLCB0, pmlcb);
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break;
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case 1:
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mtpmr(PMRN_PMLCA1, pmlca);
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mtpmr(PMRN_PMLCB1, pmlcb);
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break;
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case 2:
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mtpmr(PMRN_PMLCA2, pmlca);
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mtpmr(PMRN_PMLCB2, pmlcb);
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break;
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case 3:
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mtpmr(PMRN_PMLCA3, pmlca);
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mtpmr(PMRN_PMLCB3, pmlcb);
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break;
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default:
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panic("Bad ctr number!\n");
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}
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}
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static void set_pmc_event(int ctr, int event)
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{
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u32 pmlca;
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pmlca = get_pmlca(ctr);
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pmlca = (pmlca & ~PMLCA_EVENT_MASK) |
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((event << PMLCA_EVENT_SHIFT) &
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PMLCA_EVENT_MASK);
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set_pmlca(ctr, pmlca);
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}
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static void set_pmc_user_kernel(int ctr, int user, int kernel)
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{
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u32 pmlca;
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pmlca = get_pmlca(ctr);
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if(user)
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pmlca &= ~PMLCA_FCU;
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else
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pmlca |= PMLCA_FCU;
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if(kernel)
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pmlca &= ~PMLCA_FCS;
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else
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pmlca |= PMLCA_FCS;
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set_pmlca(ctr, pmlca);
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}
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static void set_pmc_marked(int ctr, int mark0, int mark1)
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{
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u32 pmlca = get_pmlca(ctr);
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if(mark0)
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pmlca &= ~PMLCA_FCM0;
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else
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pmlca |= PMLCA_FCM0;
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if(mark1)
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pmlca &= ~PMLCA_FCM1;
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else
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pmlca |= PMLCA_FCM1;
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set_pmlca(ctr, pmlca);
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}
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static void pmc_start_ctr(int ctr, int enable)
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{
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u32 pmlca = get_pmlca(ctr);
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pmlca &= ~PMLCA_FC;
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if (enable)
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pmlca |= PMLCA_CE;
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else
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pmlca &= ~PMLCA_CE;
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set_pmlca(ctr, pmlca);
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}
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static void pmc_start_ctrs(int enable)
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{
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u32 pmgc0 = mfpmr(PMRN_PMGC0);
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pmgc0 &= ~PMGC0_FAC;
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pmgc0 |= PMGC0_FCECE;
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if (enable)
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pmgc0 |= PMGC0_PMIE;
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else
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pmgc0 &= ~PMGC0_PMIE;
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mtpmr(PMRN_PMGC0, pmgc0);
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}
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static void pmc_stop_ctrs(void)
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{
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u32 pmgc0 = mfpmr(PMRN_PMGC0);
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pmgc0 |= PMGC0_FAC;
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pmgc0 &= ~(PMGC0_PMIE | PMGC0_FCECE);
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mtpmr(PMRN_PMGC0, pmgc0);
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}
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static int fsl_emb_cpu_setup(struct op_counter_config *ctr)
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{
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int i;
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/* freeze all counters */
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pmc_stop_ctrs();
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for (i = 0;i < num_counters;i++) {
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init_pmc_stop(i);
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set_pmc_event(i, ctr[i].event);
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set_pmc_user_kernel(i, ctr[i].user, ctr[i].kernel);
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}
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return 0;
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}
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static int fsl_emb_reg_setup(struct op_counter_config *ctr,
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struct op_system_config *sys,
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int num_ctrs)
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{
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int i;
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num_counters = num_ctrs;
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/* Our counters count up, and "count" refers to
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* how much before the next interrupt, and we interrupt
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* on overflow. So we calculate the starting value
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* which will give us "count" until overflow.
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* Then we set the events on the enabled counters */
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for (i = 0; i < num_counters; ++i)
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reset_value[i] = 0x80000000UL - ctr[i].count;
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return 0;
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}
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static int fsl_emb_start(struct op_counter_config *ctr)
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{
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int i;
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mtmsr(mfmsr() | MSR_PMM);
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for (i = 0; i < num_counters; ++i) {
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if (ctr[i].enabled) {
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ctr_write(i, reset_value[i]);
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/* Set each enabled counter to only
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* count when the Mark bit is *not* set */
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set_pmc_marked(i, 1, 0);
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pmc_start_ctr(i, 1);
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} else {
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ctr_write(i, 0);
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/* Set the ctr to be stopped */
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pmc_start_ctr(i, 0);
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}
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}
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/* Clear the freeze bit, and enable the interrupt.
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* The counters won't actually start until the rfi clears
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* the PMM bit */
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pmc_start_ctrs(1);
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oprofile_running = 1;
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pr_debug("start on cpu %d, pmgc0 %x\n", smp_processor_id(),
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mfpmr(PMRN_PMGC0));
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return 0;
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}
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static void fsl_emb_stop(void)
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{
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/* freeze counters */
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pmc_stop_ctrs();
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oprofile_running = 0;
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pr_debug("stop on cpu %d, pmgc0 %x\n", smp_processor_id(),
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mfpmr(PMRN_PMGC0));
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mb();
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}
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static void fsl_emb_handle_interrupt(struct pt_regs *regs,
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struct op_counter_config *ctr)
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{
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unsigned long pc;
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int is_kernel;
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int val;
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int i;
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pc = regs->nip;
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is_kernel = is_kernel_addr(pc);
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for (i = 0; i < num_counters; ++i) {
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val = ctr_read(i);
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if (val < 0) {
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if (oprofile_running && ctr[i].enabled) {
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oprofile_add_ext_sample(pc, regs, i, is_kernel);
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ctr_write(i, reset_value[i]);
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} else {
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ctr_write(i, 0);
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}
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}
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}
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/* The freeze bit was set by the interrupt. */
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/* Clear the freeze bit, and reenable the interrupt. The
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* counters won't actually start until the rfi clears the PMM
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* bit. The PMM bit should not be set until after the interrupt
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* is cleared to avoid it getting lost in some hypervisor
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* environments.
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*/
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mtmsr(mfmsr() | MSR_PMM);
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pmc_start_ctrs(1);
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}
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struct op_powerpc_model op_model_fsl_emb = {
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.reg_setup = fsl_emb_reg_setup,
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.cpu_setup = fsl_emb_cpu_setup,
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.start = fsl_emb_start,
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.stop = fsl_emb_stop,
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.handle_interrupt = fsl_emb_handle_interrupt,
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};
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