f54bef9e9c
Update the cpci690 platform code: - pass mem size in from bootwrapper via bi_rec - some minor fixups Signed-off-by: Mark A. Greer <mgreer@mvista.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
77 lines
2.4 KiB
C
77 lines
2.4 KiB
C
/*
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* arch/ppc/platforms/cpci690.h
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*
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* Definitions for Force CPCI690
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*
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* Author: Mark A. Greer <mgreer@mvista.com>
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*
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* 2003 (c) MontaVista, Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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/*
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* The GT64260 has 2 PCI buses each with 1 window from the CPU bus to
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* PCI I/O space and 4 windows from the CPU bus to PCI MEM space.
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*/
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#ifndef __PPC_PLATFORMS_CPCI690_H
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#define __PPC_PLATFORMS_CPCI690_H
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/*
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* Define bd_t to pass in the MAC addresses used by the GT64260's enet ctlrs.
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*/
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#define CPCI690_BI_MAGIC 0xFE8765DC
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typedef struct board_info {
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u32 bi_magic;
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u8 bi_enetaddr[3][6];
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} bd_t;
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/* PCI bus Resource setup */
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#define CPCI690_PCI0_MEM_START_PROC_ADDR 0x80000000
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#define CPCI690_PCI0_MEM_START_PCI_HI_ADDR 0x00000000
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#define CPCI690_PCI0_MEM_START_PCI_LO_ADDR 0x80000000
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#define CPCI690_PCI0_MEM_SIZE 0x10000000
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#define CPCI690_PCI0_IO_START_PROC_ADDR 0xa0000000
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#define CPCI690_PCI0_IO_START_PCI_ADDR 0x00000000
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#define CPCI690_PCI0_IO_SIZE 0x01000000
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#define CPCI690_PCI1_MEM_START_PROC_ADDR 0x90000000
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#define CPCI690_PCI1_MEM_START_PCI_HI_ADDR 0x00000000
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#define CPCI690_PCI1_MEM_START_PCI_LO_ADDR 0x90000000
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#define CPCI690_PCI1_MEM_SIZE 0x10000000
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#define CPCI690_PCI1_IO_START_PROC_ADDR 0xa1000000
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#define CPCI690_PCI1_IO_START_PCI_ADDR 0x01000000
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#define CPCI690_PCI1_IO_SIZE 0x01000000
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/* Board Registers */
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#define CPCI690_BR_BASE 0xf0000000
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#define CPCI690_BR_SIZE_ACTUAL 0x8
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#define CPCI690_BR_SIZE max(GT64260_WINDOW_SIZE_MIN, \
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CPCI690_BR_SIZE_ACTUAL)
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#define CPCI690_BR_LED_CNTL 0x00
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#define CPCI690_BR_SW_RESET 0x01
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#define CPCI690_BR_MISC_STATUS 0x02
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#define CPCI690_BR_SWITCH_STATUS 0x03
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#define CPCI690_BR_MEM_CTLR 0x04
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#define CPCI690_BR_LAST_RESET_1 0x05
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#define CPCI690_BR_LAST_RESET_2 0x06
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#define CPCI690_TODC_BASE 0xf0100000
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#define CPCI690_TODC_SIZE_ACTUAL 0x8000 /* Size or NVRAM + RTC */
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#define CPCI690_TODC_SIZE max(GT64260_WINDOW_SIZE_MIN, \
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CPCI690_TODC_SIZE_ACTUAL)
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#define CPCI690_MAC_OFFSET 0x7c10 /* MAC in RTC NVRAM */
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#define CPCI690_IPMI_BASE 0xf0200000
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#define CPCI690_IPMI_SIZE_ACTUAL 0x10 /* 16 bytes of IPMI */
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#define CPCI690_IPMI_SIZE max(GT64260_WINDOW_SIZE_MIN, \
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CPCI690_IPMI_SIZE_ACTUAL)
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#define CPCI690_MPSC_BAUD 9600
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#define CPCI690_MPSC_CLK_SRC 8 /* TCLK */
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#endif /* __PPC_PLATFORMS_CPCI690_H */
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