598f22e11b
This patch incorporates some updates from the review of the Renesas m66592-udc driver. Updates include: - Fix some locking bugs; and add a few sparse annotations - Don't #define __iomem ! - Lots of whitespace fixes (most of the patch by volume) - Some #include file trimmage - Other checkpatch.pl and sparse updates - Alphabetized and slightly-more-informative Kconfig - Don't use the ID which was assigned to the amd5536udc driver. - Remove pointless suspend/resume methods updating obsolete field. - Some section fixups - Fix some leak bugs - Fix byteswapping Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
576 lines
22 KiB
C
576 lines
22 KiB
C
/*
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* M66592 UDC (USB gadget)
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*
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* Copyright (C) 2006-2007 Renesas Solutions Corp.
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*
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* Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*
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*/
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#ifndef __M66592_UDC_H__
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#define __M66592_UDC_H__
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#define M66592_SYSCFG 0x00
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#define M66592_XTAL 0xC000 /* b15-14: Crystal selection */
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#define M66592_XTAL48 0x8000 /* 48MHz */
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#define M66592_XTAL24 0x4000 /* 24MHz */
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#define M66592_XTAL12 0x0000 /* 12MHz */
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#define M66592_XCKE 0x2000 /* b13: External clock enable */
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#define M66592_RCKE 0x1000 /* b12: Register clock enable */
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#define M66592_PLLC 0x0800 /* b11: PLL control */
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#define M66592_SCKE 0x0400 /* b10: USB clock enable */
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#define M66592_ATCKM 0x0100 /* b8: Automatic clock supply */
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#define M66592_HSE 0x0080 /* b7: Hi-speed enable */
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#define M66592_DCFM 0x0040 /* b6: Controller function select */
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#define M66592_DMRPD 0x0020 /* b5: D- pull down control */
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#define M66592_DPRPU 0x0010 /* b4: D+ pull up control */
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#define M66592_FSRPC 0x0004 /* b2: Full-speed receiver enable */
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#define M66592_PCUT 0x0002 /* b1: Low power sleep enable */
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#define M66592_USBE 0x0001 /* b0: USB module operation enable */
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#define M66592_SYSSTS 0x02
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#define M66592_LNST 0x0003 /* b1-0: D+, D- line status */
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#define M66592_SE1 0x0003 /* SE1 */
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#define M66592_KSTS 0x0002 /* K State */
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#define M66592_JSTS 0x0001 /* J State */
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#define M66592_SE0 0x0000 /* SE0 */
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#define M66592_DVSTCTR 0x04
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#define M66592_WKUP 0x0100 /* b8: Remote wakeup */
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#define M66592_RWUPE 0x0080 /* b7: Remote wakeup sense */
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#define M66592_USBRST 0x0040 /* b6: USB reset enable */
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#define M66592_RESUME 0x0020 /* b5: Resume enable */
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#define M66592_UACT 0x0010 /* b4: USB bus enable */
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#define M66592_RHST 0x0003 /* b1-0: Reset handshake status */
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#define M66592_HSMODE 0x0003 /* Hi-Speed mode */
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#define M66592_FSMODE 0x0002 /* Full-Speed mode */
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#define M66592_HSPROC 0x0001 /* HS handshake is processing */
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#define M66592_TESTMODE 0x06
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#define M66592_UTST 0x000F /* b4-0: Test select */
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#define M66592_H_TST_PACKET 0x000C /* HOST TEST Packet */
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#define M66592_H_TST_SE0_NAK 0x000B /* HOST TEST SE0 NAK */
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#define M66592_H_TST_K 0x000A /* HOST TEST K */
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#define M66592_H_TST_J 0x0009 /* HOST TEST J */
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#define M66592_H_TST_NORMAL 0x0000 /* HOST Normal Mode */
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#define M66592_P_TST_PACKET 0x0004 /* PERI TEST Packet */
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#define M66592_P_TST_SE0_NAK 0x0003 /* PERI TEST SE0 NAK */
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#define M66592_P_TST_K 0x0002 /* PERI TEST K */
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#define M66592_P_TST_J 0x0001 /* PERI TEST J */
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#define M66592_P_TST_NORMAL 0x0000 /* PERI Normal Mode */
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#define M66592_PINCFG 0x0A
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#define M66592_LDRV 0x8000 /* b15: Drive Current Adjust */
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#define M66592_BIGEND 0x0100 /* b8: Big endian mode */
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#define M66592_DMA0CFG 0x0C
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#define M66592_DMA1CFG 0x0E
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#define M66592_DREQA 0x4000 /* b14: Dreq active select */
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#define M66592_BURST 0x2000 /* b13: Burst mode */
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#define M66592_DACKA 0x0400 /* b10: Dack active select */
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#define M66592_DFORM 0x0380 /* b9-7: DMA mode select */
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#define M66592_CPU_ADR_RD_WR 0x0000 /* Address + RD/WR mode (CPU bus) */
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#define M66592_CPU_DACK_RD_WR 0x0100 /* DACK + RD/WR mode (CPU bus) */
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#define M66592_CPU_DACK_ONLY 0x0180 /* DACK only mode (CPU bus) */
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#define M66592_SPLIT_DACK_ONLY 0x0200 /* DACK only mode (SPLIT bus) */
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#define M66592_SPLIT_DACK_DSTB 0x0300 /* DACK + DSTB0 mode (SPLIT bus) */
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#define M66592_DENDA 0x0040 /* b6: Dend active select */
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#define M66592_PKTM 0x0020 /* b5: Packet mode */
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#define M66592_DENDE 0x0010 /* b4: Dend enable */
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#define M66592_OBUS 0x0004 /* b2: OUTbus mode */
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#define M66592_CFIFO 0x10
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#define M66592_D0FIFO 0x14
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#define M66592_D1FIFO 0x18
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#define M66592_CFIFOSEL 0x1E
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#define M66592_D0FIFOSEL 0x24
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#define M66592_D1FIFOSEL 0x2A
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#define M66592_RCNT 0x8000 /* b15: Read count mode */
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#define M66592_REW 0x4000 /* b14: Buffer rewind */
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#define M66592_DCLRM 0x2000 /* b13: DMA buffer clear mode */
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#define M66592_DREQE 0x1000 /* b12: DREQ output enable */
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#define M66592_MBW 0x0400 /* b10: Maximum bit width for FIFO */
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#define M66592_MBW_8 0x0000 /* 8bit */
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#define M66592_MBW_16 0x0400 /* 16bit */
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#define M66592_TRENB 0x0200 /* b9: Transaction counter enable */
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#define M66592_TRCLR 0x0100 /* b8: Transaction counter clear */
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#define M66592_DEZPM 0x0080 /* b7: Zero-length packet mode */
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#define M66592_ISEL 0x0020 /* b5: DCP FIFO port direction select */
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#define M66592_CURPIPE 0x0007 /* b2-0: PIPE select */
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#define M66592_CFIFOCTR 0x20
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#define M66592_D0FIFOCTR 0x26
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#define M66592_D1FIFOCTR 0x2c
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#define M66592_BVAL 0x8000 /* b15: Buffer valid flag */
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#define M66592_BCLR 0x4000 /* b14: Buffer clear */
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#define M66592_FRDY 0x2000 /* b13: FIFO ready */
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#define M66592_DTLN 0x0FFF /* b11-0: FIFO received data length */
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#define M66592_CFIFOSIE 0x22
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#define M66592_TGL 0x8000 /* b15: Buffer toggle */
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#define M66592_SCLR 0x4000 /* b14: Buffer clear */
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#define M66592_SBUSY 0x2000 /* b13: SIE_FIFO busy */
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#define M66592_D0FIFOTRN 0x28
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#define M66592_D1FIFOTRN 0x2E
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#define M66592_TRNCNT 0xFFFF /* b15-0: Transaction counter */
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#define M66592_INTENB0 0x30
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#define M66592_VBSE 0x8000 /* b15: VBUS interrupt */
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#define M66592_RSME 0x4000 /* b14: Resume interrupt */
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#define M66592_SOFE 0x2000 /* b13: Frame update interrupt */
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#define M66592_DVSE 0x1000 /* b12: Device state transition interrupt */
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#define M66592_CTRE 0x0800 /* b11: Control transfer stage transition irq */
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#define M66592_BEMPE 0x0400 /* b10: Buffer empty interrupt */
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#define M66592_NRDYE 0x0200 /* b9: Buffer not ready interrupt */
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#define M66592_BRDYE 0x0100 /* b8: Buffer ready interrupt */
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#define M66592_URST 0x0080 /* b7: USB reset detected interrupt */
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#define M66592_SADR 0x0040 /* b6: Set address executed interrupt */
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#define M66592_SCFG 0x0020 /* b5: Set configuration executed interrupt */
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#define M66592_SUSP 0x0010 /* b4: Suspend detected interrupt */
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#define M66592_WDST 0x0008 /* b3: Control write data stage completed irq */
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#define M66592_RDST 0x0004 /* b2: Control read data stage completed irq */
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#define M66592_CMPL 0x0002 /* b1: Control transfer complete interrupt */
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#define M66592_SERR 0x0001 /* b0: Sequence error interrupt */
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#define M66592_INTENB1 0x32
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#define M66592_BCHGE 0x4000 /* b14: USB us chenge interrupt */
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#define M66592_DTCHE 0x1000 /* b12: Detach sense interrupt */
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#define M66592_SIGNE 0x0020 /* b5: SETUP IGNORE interrupt */
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#define M66592_SACKE 0x0010 /* b4: SETUP ACK interrupt */
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#define M66592_BRDYM 0x0004 /* b2: BRDY clear timing */
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#define M66592_INTL 0x0002 /* b1: Interrupt sense select */
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#define M66592_PCSE 0x0001 /* b0: PCUT enable by CS assert */
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#define M66592_BRDYENB 0x36
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#define M66592_BRDYSTS 0x46
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#define M66592_BRDY7 0x0080 /* b7: PIPE7 */
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#define M66592_BRDY6 0x0040 /* b6: PIPE6 */
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#define M66592_BRDY5 0x0020 /* b5: PIPE5 */
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#define M66592_BRDY4 0x0010 /* b4: PIPE4 */
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#define M66592_BRDY3 0x0008 /* b3: PIPE3 */
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#define M66592_BRDY2 0x0004 /* b2: PIPE2 */
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#define M66592_BRDY1 0x0002 /* b1: PIPE1 */
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#define M66592_BRDY0 0x0001 /* b1: PIPE0 */
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#define M66592_NRDYENB 0x38
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#define M66592_NRDYSTS 0x48
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#define M66592_NRDY7 0x0080 /* b7: PIPE7 */
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#define M66592_NRDY6 0x0040 /* b6: PIPE6 */
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#define M66592_NRDY5 0x0020 /* b5: PIPE5 */
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#define M66592_NRDY4 0x0010 /* b4: PIPE4 */
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#define M66592_NRDY3 0x0008 /* b3: PIPE3 */
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#define M66592_NRDY2 0x0004 /* b2: PIPE2 */
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#define M66592_NRDY1 0x0002 /* b1: PIPE1 */
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#define M66592_NRDY0 0x0001 /* b1: PIPE0 */
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#define M66592_BEMPENB 0x3A
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#define M66592_BEMPSTS 0x4A
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#define M66592_BEMP7 0x0080 /* b7: PIPE7 */
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#define M66592_BEMP6 0x0040 /* b6: PIPE6 */
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#define M66592_BEMP5 0x0020 /* b5: PIPE5 */
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#define M66592_BEMP4 0x0010 /* b4: PIPE4 */
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#define M66592_BEMP3 0x0008 /* b3: PIPE3 */
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#define M66592_BEMP2 0x0004 /* b2: PIPE2 */
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#define M66592_BEMP1 0x0002 /* b1: PIPE1 */
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#define M66592_BEMP0 0x0001 /* b0: PIPE0 */
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#define M66592_SOFCFG 0x3C
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#define M66592_SOFM 0x000C /* b3-2: SOF palse mode */
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#define M66592_SOF_125US 0x0008 /* SOF OUT 125us uFrame Signal */
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#define M66592_SOF_1MS 0x0004 /* SOF OUT 1ms Frame Signal */
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#define M66592_SOF_DISABLE 0x0000 /* SOF OUT Disable */
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#define M66592_INTSTS0 0x40
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#define M66592_VBINT 0x8000 /* b15: VBUS interrupt */
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#define M66592_RESM 0x4000 /* b14: Resume interrupt */
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#define M66592_SOFR 0x2000 /* b13: SOF frame update interrupt */
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#define M66592_DVST 0x1000 /* b12: Device state transition */
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#define M66592_CTRT 0x0800 /* b11: Control stage transition */
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#define M66592_BEMP 0x0400 /* b10: Buffer empty interrupt */
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#define M66592_NRDY 0x0200 /* b9: Buffer not ready interrupt */
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#define M66592_BRDY 0x0100 /* b8: Buffer ready interrupt */
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#define M66592_VBSTS 0x0080 /* b7: VBUS input port */
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#define M66592_DVSQ 0x0070 /* b6-4: Device state */
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#define M66592_DS_SPD_CNFG 0x0070 /* Suspend Configured */
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#define M66592_DS_SPD_ADDR 0x0060 /* Suspend Address */
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#define M66592_DS_SPD_DFLT 0x0050 /* Suspend Default */
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#define M66592_DS_SPD_POWR 0x0040 /* Suspend Powered */
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#define M66592_DS_SUSP 0x0040 /* Suspend */
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#define M66592_DS_CNFG 0x0030 /* Configured */
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#define M66592_DS_ADDS 0x0020 /* Address */
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#define M66592_DS_DFLT 0x0010 /* Default */
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#define M66592_DS_POWR 0x0000 /* Powered */
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#define M66592_DVSQS 0x0030 /* b5-4: Device state */
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#define M66592_VALID 0x0008 /* b3: Setup packet detected flag */
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#define M66592_CTSQ 0x0007 /* b2-0: Control transfer stage */
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#define M66592_CS_SQER 0x0006 /* Sequence error */
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#define M66592_CS_WRND 0x0005 /* Control write nodata status */
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#define M66592_CS_WRSS 0x0004 /* Control write status stage */
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#define M66592_CS_WRDS 0x0003 /* Control write data stage */
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#define M66592_CS_RDSS 0x0002 /* Control read status stage */
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#define M66592_CS_RDDS 0x0001 /* Control read data stage */
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#define M66592_CS_IDST 0x0000 /* Idle or setup stage */
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#define M66592_INTSTS1 0x42
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#define M66592_BCHG 0x4000 /* b14: USB bus chenge interrupt */
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#define M66592_DTCH 0x1000 /* b12: Detach sense interrupt */
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#define M66592_SIGN 0x0020 /* b5: SETUP IGNORE interrupt */
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#define M66592_SACK 0x0010 /* b4: SETUP ACK interrupt */
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#define M66592_FRMNUM 0x4C
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#define M66592_OVRN 0x8000 /* b15: Overrun error */
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#define M66592_CRCE 0x4000 /* b14: Received data error */
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#define M66592_SOFRM 0x0800 /* b11: SOF output mode */
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#define M66592_FRNM 0x07FF /* b10-0: Frame number */
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#define M66592_UFRMNUM 0x4E
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#define M66592_UFRNM 0x0007 /* b2-0: Micro frame number */
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#define M66592_RECOVER 0x50
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#define M66592_STSRECOV 0x0700 /* Status recovery */
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#define M66592_STSR_HI 0x0400 /* FULL(0) or HI(1) Speed */
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#define M66592_STSR_DEFAULT 0x0100 /* Default state */
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#define M66592_STSR_ADDRESS 0x0200 /* Address state */
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#define M66592_STSR_CONFIG 0x0300 /* Configured state */
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#define M66592_USBADDR 0x007F /* b6-0: USB address */
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#define M66592_USBREQ 0x54
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#define M66592_bRequest 0xFF00 /* b15-8: bRequest */
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#define M66592_GET_STATUS 0x0000
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#define M66592_CLEAR_FEATURE 0x0100
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#define M66592_ReqRESERVED 0x0200
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#define M66592_SET_FEATURE 0x0300
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#define M66592_ReqRESERVED1 0x0400
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#define M66592_SET_ADDRESS 0x0500
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#define M66592_GET_DESCRIPTOR 0x0600
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#define M66592_SET_DESCRIPTOR 0x0700
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#define M66592_GET_CONFIGURATION 0x0800
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#define M66592_SET_CONFIGURATION 0x0900
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#define M66592_GET_INTERFACE 0x0A00
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#define M66592_SET_INTERFACE 0x0B00
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#define M66592_SYNCH_FRAME 0x0C00
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#define M66592_bmRequestType 0x00FF /* b7-0: bmRequestType */
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#define M66592_bmRequestTypeDir 0x0080 /* b7 : Data direction */
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#define M66592_HOST_TO_DEVICE 0x0000
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#define M66592_DEVICE_TO_HOST 0x0080
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#define M66592_bmRequestTypeType 0x0060 /* b6-5: Type */
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#define M66592_STANDARD 0x0000
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#define M66592_CLASS 0x0020
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#define M66592_VENDOR 0x0040
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#define M66592_bmRequestTypeRecip 0x001F /* b4-0: Recipient */
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#define M66592_DEVICE 0x0000
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#define M66592_INTERFACE 0x0001
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#define M66592_ENDPOINT 0x0002
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#define M66592_USBVAL 0x56
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#define M66592_wValue 0xFFFF /* b15-0: wValue */
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/* Standard Feature Selector */
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#define M66592_ENDPOINT_HALT 0x0000
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#define M66592_DEVICE_REMOTE_WAKEUP 0x0001
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#define M66592_TEST_MODE 0x0002
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/* Descriptor Types */
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#define M66592_DT_TYPE 0xFF00
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#define M66592_GET_DT_TYPE(v) (((v) & DT_TYPE) >> 8)
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#define M66592_DT_DEVICE 0x01
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#define M66592_DT_CONFIGURATION 0x02
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#define M66592_DT_STRING 0x03
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#define M66592_DT_INTERFACE 0x04
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#define M66592_DT_ENDPOINT 0x05
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#define M66592_DT_DEVICE_QUALIFIER 0x06
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#define M66592_DT_OTHER_SPEED_CONFIGURATION 0x07
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#define M66592_DT_INTERFACE_POWER 0x08
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#define M66592_DT_INDEX 0x00FF
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#define M66592_CONF_NUM 0x00FF
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#define M66592_ALT_SET 0x00FF
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#define M66592_USBINDEX 0x58
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#define M66592_wIndex 0xFFFF /* b15-0: wIndex */
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#define M66592_TEST_SELECT 0xFF00 /* b15-b8: Test Mode */
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#define M66592_TEST_J 0x0100 /* Test_J */
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#define M66592_TEST_K 0x0200 /* Test_K */
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#define M66592_TEST_SE0_NAK 0x0300 /* Test_SE0_NAK */
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#define M66592_TEST_PACKET 0x0400 /* Test_Packet */
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#define M66592_TEST_FORCE_ENABLE 0x0500 /* Test_Force_Enable */
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#define M66592_TEST_STSelectors 0x0600 /* Standard test selectors */
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#define M66592_TEST_Reserved 0x4000 /* Reserved */
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#define M66592_TEST_VSTModes 0xC000 /* Vendor-specific tests */
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#define M66592_EP_DIR 0x0080 /* b7: Endpoint Direction */
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#define M66592_EP_DIR_IN 0x0080
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#define M66592_EP_DIR_OUT 0x0000
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#define M66592_USBLENG 0x5A
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#define M66592_wLength 0xFFFF /* b15-0: wLength */
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#define M66592_DCPCFG 0x5C
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#define M66592_CNTMD 0x0100 /* b8: Continuous transfer mode */
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#define M66592_DIR 0x0010 /* b4: Control transfer DIR select */
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#define M66592_DCPMAXP 0x5E
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#define M66592_DEVSEL 0xC000 /* b15-14: Device address select */
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#define M66592_DEVICE_0 0x0000 /* Device address 0 */
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#define M66592_DEVICE_1 0x4000 /* Device address 1 */
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#define M66592_DEVICE_2 0x8000 /* Device address 2 */
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#define M66592_DEVICE_3 0xC000 /* Device address 3 */
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#define M66592_MAXP 0x007F /* b6-0: Maxpacket size of ep0 */
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#define M66592_DCPCTR 0x60
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#define M66592_BSTS 0x8000 /* b15: Buffer status */
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#define M66592_SUREQ 0x4000 /* b14: Send USB request */
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#define M66592_SQCLR 0x0100 /* b8: Sequence toggle bit clear */
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#define M66592_SQSET 0x0080 /* b7: Sequence toggle bit set */
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#define M66592_SQMON 0x0040 /* b6: Sequence toggle bit monitor */
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#define M66592_CCPL 0x0004 /* b2: control transfer complete */
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#define M66592_PID 0x0003 /* b1-0: Response PID */
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#define M66592_PID_STALL 0x0002 /* STALL */
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#define M66592_PID_BUF 0x0001 /* BUF */
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#define M66592_PID_NAK 0x0000 /* NAK */
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#define M66592_PIPESEL 0x64
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#define M66592_PIPENM 0x0007 /* b2-0: Pipe select */
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#define M66592_PIPE0 0x0000 /* PIPE 0 */
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#define M66592_PIPE1 0x0001 /* PIPE 1 */
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#define M66592_PIPE2 0x0002 /* PIPE 2 */
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#define M66592_PIPE3 0x0003 /* PIPE 3 */
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#define M66592_PIPE4 0x0004 /* PIPE 4 */
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#define M66592_PIPE5 0x0005 /* PIPE 5 */
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#define M66592_PIPE6 0x0006 /* PIPE 6 */
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#define M66592_PIPE7 0x0007 /* PIPE 7 */
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#define M66592_PIPECFG 0x66
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#define M66592_TYP 0xC000 /* b15-14: Transfer type */
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#define M66592_ISO 0xC000 /* Isochronous */
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#define M66592_INT 0x8000 /* Interrupt */
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#define M66592_BULK 0x4000 /* Bulk */
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#define M66592_BFRE 0x0400 /* b10: Buffer ready interrupt mode */
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#define M66592_DBLB 0x0200 /* b9: Double buffer mode select */
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#define M66592_CNTMD 0x0100 /* b8: Continuous transfer mode */
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#define M66592_SHTNAK 0x0080 /* b7: Transfer end NAK */
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#define M66592_DIR 0x0010 /* b4: Transfer direction select */
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#define M66592_DIR_H_OUT 0x0010 /* HOST OUT */
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#define M66592_DIR_P_IN 0x0010 /* PERI IN */
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#define M66592_DIR_H_IN 0x0000 /* HOST IN */
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#define M66592_DIR_P_OUT 0x0000 /* PERI OUT */
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#define M66592_EPNUM 0x000F /* b3-0: Eendpoint number select */
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#define M66592_EP1 0x0001
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#define M66592_EP2 0x0002
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#define M66592_EP3 0x0003
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#define M66592_EP4 0x0004
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#define M66592_EP5 0x0005
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#define M66592_EP6 0x0006
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#define M66592_EP7 0x0007
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#define M66592_EP8 0x0008
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#define M66592_EP9 0x0009
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#define M66592_EP10 0x000A
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#define M66592_EP11 0x000B
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#define M66592_EP12 0x000C
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#define M66592_EP13 0x000D
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#define M66592_EP14 0x000E
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#define M66592_EP15 0x000F
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#define M66592_PIPEBUF 0x68
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#define M66592_BUFSIZE 0x7C00 /* b14-10: Pipe buffer size */
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#define M66592_BUF_SIZE(x) ((((x) / 64) - 1) << 10)
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#define M66592_BUFNMB 0x00FF /* b7-0: Pipe buffer number */
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#define M66592_PIPEMAXP 0x6A
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#define M66592_MXPS 0x07FF /* b10-0: Maxpacket size */
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#define M66592_PIPEPERI 0x6C
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#define M66592_IFIS 0x1000 /* b12: ISO in-buffer flush mode */
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#define M66592_IITV 0x0007 /* b2-0: ISO interval */
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#define M66592_PIPE1CTR 0x70
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#define M66592_PIPE2CTR 0x72
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#define M66592_PIPE3CTR 0x74
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#define M66592_PIPE4CTR 0x76
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#define M66592_PIPE5CTR 0x78
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#define M66592_PIPE6CTR 0x7A
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#define M66592_PIPE7CTR 0x7C
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#define M66592_BSTS 0x8000 /* b15: Buffer status */
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#define M66592_INBUFM 0x4000 /* b14: IN buffer monitor (PIPE 1-5) */
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#define M66592_ACLRM 0x0200 /* b9: Out buffer auto clear mode */
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#define M66592_SQCLR 0x0100 /* b8: Sequence toggle bit clear */
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#define M66592_SQSET 0x0080 /* b7: Sequence toggle bit set */
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#define M66592_SQMON 0x0040 /* b6: Sequence toggle bit monitor */
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#define M66592_PID 0x0003 /* b1-0: Response PID */
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#define M66592_INVALID_REG 0x7E
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#define get_pipectr_addr(pipenum) (M66592_PIPE1CTR + (pipenum - 1) * 2)
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#define M66592_MAX_SAMPLING 10
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#define M66592_MAX_NUM_PIPE 8
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#define M66592_MAX_NUM_BULK 3
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#define M66592_MAX_NUM_ISOC 2
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#define M66592_MAX_NUM_INT 2
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#define M66592_BASE_PIPENUM_BULK 3
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#define M66592_BASE_PIPENUM_ISOC 1
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#define M66592_BASE_PIPENUM_INT 6
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#define M66592_BASE_BUFNUM 6
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#define M66592_MAX_BUFNUM 0x4F
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struct m66592_pipe_info {
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u16 pipe;
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u16 epnum;
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u16 maxpacket;
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u16 type;
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u16 interval;
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u16 dir_in;
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};
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struct m66592_request {
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struct usb_request req;
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struct list_head queue;
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};
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struct m66592_ep {
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struct usb_ep ep;
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struct m66592 *m66592;
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struct list_head queue;
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unsigned busy:1;
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unsigned internal_ccpl:1; /* use only control */
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|
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/* this member can able to after m66592_enable */
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unsigned use_dma:1;
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|
u16 pipenum;
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|
u16 type;
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|
const struct usb_endpoint_descriptor *desc;
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|
/* register address */
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|
unsigned long fifoaddr;
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|
unsigned long fifosel;
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|
unsigned long fifoctr;
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unsigned long fifotrn;
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unsigned long pipectr;
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};
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struct m66592 {
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spinlock_t lock;
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void __iomem *reg;
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struct usb_gadget gadget;
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struct usb_gadget_driver *driver;
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struct m66592_ep ep[M66592_MAX_NUM_PIPE];
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struct m66592_ep *pipenum2ep[M66592_MAX_NUM_PIPE];
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struct m66592_ep *epaddr2ep[16];
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struct usb_request *ep0_req; /* for internal request */
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|
u16 ep0_data; /* for internal request */
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|
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|
struct timer_list timer;
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|
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|
u16 old_vbus;
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|
int scount;
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|
|
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int old_dvsq;
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|
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/* pipe config */
|
|
int bulk;
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|
int interrupt;
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|
int isochronous;
|
|
int num_dma;
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|
int bi_bufnum; /* bulk and isochronous's bufnum */
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|
};
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|
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#define gadget_to_m66592(_gadget) container_of(_gadget, struct m66592, gadget)
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#define m66592_to_gadget(m66592) (&m66592->gadget)
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#define is_bulk_pipe(pipenum) \
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((pipenum >= M66592_BASE_PIPENUM_BULK) && \
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(pipenum < (M66592_BASE_PIPENUM_BULK + M66592_MAX_NUM_BULK)))
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#define is_interrupt_pipe(pipenum) \
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((pipenum >= M66592_BASE_PIPENUM_INT) && \
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(pipenum < (M66592_BASE_PIPENUM_INT + M66592_MAX_NUM_INT)))
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#define is_isoc_pipe(pipenum) \
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((pipenum >= M66592_BASE_PIPENUM_ISOC) && \
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|
(pipenum < (M66592_BASE_PIPENUM_ISOC + M66592_MAX_NUM_ISOC)))
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#define enable_irq_ready(m66592, pipenum) \
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enable_pipe_irq(m66592, pipenum, M66592_BRDYENB)
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#define disable_irq_ready(m66592, pipenum) \
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disable_pipe_irq(m66592, pipenum, M66592_BRDYENB)
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#define enable_irq_empty(m66592, pipenum) \
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enable_pipe_irq(m66592, pipenum, M66592_BEMPENB)
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#define disable_irq_empty(m66592, pipenum) \
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disable_pipe_irq(m66592, pipenum, M66592_BEMPENB)
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#define enable_irq_nrdy(m66592, pipenum) \
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enable_pipe_irq(m66592, pipenum, M66592_NRDYENB)
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#define disable_irq_nrdy(m66592, pipenum) \
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disable_pipe_irq(m66592, pipenum, M66592_NRDYENB)
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|
|
|
/*-------------------------------------------------------------------------*/
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|
static inline u16 m66592_read(struct m66592 *m66592, unsigned long offset)
|
|
{
|
|
return inw((unsigned long)m66592->reg + offset);
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|
}
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|
|
|
static inline void m66592_read_fifo(struct m66592 *m66592,
|
|
unsigned long offset,
|
|
void *buf, unsigned long len)
|
|
{
|
|
unsigned long fifoaddr = (unsigned long)m66592->reg + offset;
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|
|
|
len = (len + 1) / 2;
|
|
insw(fifoaddr, buf, len);
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|
}
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|
|
|
static inline void m66592_write(struct m66592 *m66592, u16 val,
|
|
unsigned long offset)
|
|
{
|
|
outw(val, (unsigned long)m66592->reg + offset);
|
|
}
|
|
|
|
static inline void m66592_write_fifo(struct m66592 *m66592,
|
|
unsigned long offset,
|
|
void *buf, unsigned long len)
|
|
{
|
|
unsigned long fifoaddr = (unsigned long)m66592->reg + offset;
|
|
unsigned long odd = len & 0x0001;
|
|
|
|
len = len / 2;
|
|
outsw(fifoaddr, buf, len);
|
|
if (odd) {
|
|
unsigned char *p = buf + len*2;
|
|
outb(*p, fifoaddr);
|
|
}
|
|
}
|
|
|
|
static inline void m66592_mdfy(struct m66592 *m66592, u16 val, u16 pat,
|
|
unsigned long offset)
|
|
{
|
|
u16 tmp;
|
|
tmp = m66592_read(m66592, offset);
|
|
tmp = tmp & (~pat);
|
|
tmp = tmp | val;
|
|
m66592_write(m66592, tmp, offset);
|
|
}
|
|
|
|
#define m66592_bclr(m66592, val, offset) \
|
|
m66592_mdfy(m66592, 0, val, offset)
|
|
#define m66592_bset(m66592, val, offset) \
|
|
m66592_mdfy(m66592, val, 0, offset)
|
|
|
|
#endif /* ifndef __M66592_UDC_H__ */
|
|
|
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