1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
472 lines
12 KiB
C
472 lines
12 KiB
C
/*
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* linux/arch/m68k/mm/memory.c
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*
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* Copyright (C) 1995 Hamish Macdonald
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*/
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#include <linux/config.h>
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#include <linux/mm.h>
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#include <linux/kernel.h>
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#include <linux/string.h>
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#include <linux/types.h>
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#include <linux/slab.h>
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#include <linux/init.h>
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#include <linux/pagemap.h>
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#include <asm/setup.h>
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#include <asm/segment.h>
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#include <asm/page.h>
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#include <asm/pgalloc.h>
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#include <asm/system.h>
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#include <asm/traps.h>
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#include <asm/machdep.h>
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/* ++andreas: {get,free}_pointer_table rewritten to use unused fields from
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struct page instead of separately kmalloced struct. Stolen from
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arch/sparc/mm/srmmu.c ... */
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typedef struct list_head ptable_desc;
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static LIST_HEAD(ptable_list);
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#define PD_PTABLE(page) ((ptable_desc *)&(virt_to_page(page)->lru))
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#define PD_PAGE(ptable) (list_entry(ptable, struct page, lru))
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#define PD_MARKBITS(dp) (*(unsigned char *)&PD_PAGE(dp)->index)
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#define PTABLE_SIZE (PTRS_PER_PMD * sizeof(pmd_t))
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void __init init_pointer_table(unsigned long ptable)
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{
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ptable_desc *dp;
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unsigned long page = ptable & PAGE_MASK;
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unsigned char mask = 1 << ((ptable - page)/PTABLE_SIZE);
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dp = PD_PTABLE(page);
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if (!(PD_MARKBITS(dp) & mask)) {
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PD_MARKBITS(dp) = 0xff;
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list_add(dp, &ptable_list);
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}
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PD_MARKBITS(dp) &= ~mask;
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#ifdef DEBUG
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printk("init_pointer_table: %lx, %x\n", ptable, PD_MARKBITS(dp));
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#endif
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/* unreserve the page so it's possible to free that page */
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PD_PAGE(dp)->flags &= ~(1 << PG_reserved);
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set_page_count(PD_PAGE(dp), 1);
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return;
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}
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pmd_t *get_pointer_table (void)
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{
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ptable_desc *dp = ptable_list.next;
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unsigned char mask = PD_MARKBITS (dp);
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unsigned char tmp;
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unsigned int off;
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/*
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* For a pointer table for a user process address space, a
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* table is taken from a page allocated for the purpose. Each
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* page can hold 8 pointer tables. The page is remapped in
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* virtual address space to be noncacheable.
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*/
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if (mask == 0) {
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void *page;
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ptable_desc *new;
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if (!(page = (void *)get_zeroed_page(GFP_KERNEL)))
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return NULL;
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flush_tlb_kernel_page(page);
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nocache_page(page);
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new = PD_PTABLE(page);
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PD_MARKBITS(new) = 0xfe;
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list_add_tail(new, dp);
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return (pmd_t *)page;
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}
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for (tmp = 1, off = 0; (mask & tmp) == 0; tmp <<= 1, off += PTABLE_SIZE)
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;
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PD_MARKBITS(dp) = mask & ~tmp;
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if (!PD_MARKBITS(dp)) {
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/* move to end of list */
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list_del(dp);
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list_add_tail(dp, &ptable_list);
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}
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return (pmd_t *) (page_address(PD_PAGE(dp)) + off);
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}
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int free_pointer_table (pmd_t *ptable)
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{
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ptable_desc *dp;
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unsigned long page = (unsigned long)ptable & PAGE_MASK;
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unsigned char mask = 1 << (((unsigned long)ptable - page)/PTABLE_SIZE);
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dp = PD_PTABLE(page);
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if (PD_MARKBITS (dp) & mask)
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panic ("table already free!");
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PD_MARKBITS (dp) |= mask;
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if (PD_MARKBITS(dp) == 0xff) {
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/* all tables in page are free, free page */
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list_del(dp);
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cache_page((void *)page);
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free_page (page);
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return 1;
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} else if (ptable_list.next != dp) {
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/*
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* move this descriptor to the front of the list, since
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* it has one or more free tables.
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*/
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list_del(dp);
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list_add(dp, &ptable_list);
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}
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return 0;
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}
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#ifdef DEBUG_INVALID_PTOV
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int mm_inv_cnt = 5;
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#endif
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#ifndef CONFIG_SINGLE_MEMORY_CHUNK
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/*
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* The following two routines map from a physical address to a kernel
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* virtual address and vice versa.
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*/
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unsigned long mm_vtop(unsigned long vaddr)
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{
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int i=0;
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unsigned long voff = (unsigned long)vaddr - PAGE_OFFSET;
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do {
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if (voff < m68k_memory[i].size) {
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#ifdef DEBUGPV
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printk ("VTOP(%p)=%lx\n", vaddr,
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m68k_memory[i].addr + voff);
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#endif
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return m68k_memory[i].addr + voff;
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}
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voff -= m68k_memory[i].size;
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} while (++i < m68k_num_memory);
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/* As a special case allow `__pa(high_memory)'. */
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if (voff == 0)
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return m68k_memory[i-1].addr + m68k_memory[i-1].size;
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return -1;
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}
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#endif
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#ifndef CONFIG_SINGLE_MEMORY_CHUNK
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unsigned long mm_ptov (unsigned long paddr)
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{
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int i = 0;
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unsigned long poff, voff = PAGE_OFFSET;
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do {
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poff = paddr - m68k_memory[i].addr;
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if (poff < m68k_memory[i].size) {
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#ifdef DEBUGPV
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printk ("PTOV(%lx)=%lx\n", paddr, poff + voff);
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#endif
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return poff + voff;
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}
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voff += m68k_memory[i].size;
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} while (++i < m68k_num_memory);
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#ifdef DEBUG_INVALID_PTOV
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if (mm_inv_cnt > 0) {
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mm_inv_cnt--;
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printk("Invalid use of phys_to_virt(0x%lx) at 0x%p!\n",
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paddr, __builtin_return_address(0));
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}
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#endif
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return -1;
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}
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#endif
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/* invalidate page in both caches */
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static inline void clear040(unsigned long paddr)
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{
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asm volatile (
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"nop\n\t"
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".chip 68040\n\t"
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"cinvp %%bc,(%0)\n\t"
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".chip 68k"
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: : "a" (paddr));
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}
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/* invalidate page in i-cache */
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static inline void cleari040(unsigned long paddr)
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{
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asm volatile (
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"nop\n\t"
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".chip 68040\n\t"
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"cinvp %%ic,(%0)\n\t"
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".chip 68k"
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: : "a" (paddr));
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}
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/* push page in both caches */
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/* RZ: cpush %bc DOES invalidate %ic, regardless of DPI */
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static inline void push040(unsigned long paddr)
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{
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asm volatile (
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"nop\n\t"
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".chip 68040\n\t"
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"cpushp %%bc,(%0)\n\t"
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".chip 68k"
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: : "a" (paddr));
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}
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/* push and invalidate page in both caches, must disable ints
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* to avoid invalidating valid data */
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static inline void pushcl040(unsigned long paddr)
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{
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unsigned long flags;
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local_irq_save(flags);
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push040(paddr);
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if (CPU_IS_060)
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clear040(paddr);
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local_irq_restore(flags);
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}
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/*
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* 040: Hit every page containing an address in the range paddr..paddr+len-1.
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* (Low order bits of the ea of a CINVP/CPUSHP are "don't care"s).
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* Hit every page until there is a page or less to go. Hit the next page,
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* and the one after that if the range hits it.
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*/
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/* ++roman: A little bit more care is required here: The CINVP instruction
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* invalidates cache entries WITHOUT WRITING DIRTY DATA BACK! So the beginning
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* and the end of the region must be treated differently if they are not
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* exactly at the beginning or end of a page boundary. Else, maybe too much
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* data becomes invalidated and thus lost forever. CPUSHP does what we need:
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* it invalidates the page after pushing dirty data to memory. (Thanks to Jes
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* for discovering the problem!)
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*/
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/* ... but on the '060, CPUSH doesn't invalidate (for us, since we have set
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* the DPI bit in the CACR; would it cause problems with temporarily changing
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* this?). So we have to push first and then additionally to invalidate.
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*/
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/*
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* cache_clear() semantics: Clear any cache entries for the area in question,
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* without writing back dirty entries first. This is useful if the data will
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* be overwritten anyway, e.g. by DMA to memory. The range is defined by a
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* _physical_ address.
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*/
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void cache_clear (unsigned long paddr, int len)
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{
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if (CPU_IS_040_OR_060) {
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int tmp;
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/*
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* We need special treatment for the first page, in case it
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* is not page-aligned. Page align the addresses to work
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* around bug I17 in the 68060.
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*/
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if ((tmp = -paddr & (PAGE_SIZE - 1))) {
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pushcl040(paddr & PAGE_MASK);
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if ((len -= tmp) <= 0)
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return;
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paddr += tmp;
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}
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tmp = PAGE_SIZE;
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paddr &= PAGE_MASK;
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while ((len -= tmp) >= 0) {
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clear040(paddr);
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paddr += tmp;
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}
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if ((len += tmp))
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/* a page boundary gets crossed at the end */
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pushcl040(paddr);
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}
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else /* 68030 or 68020 */
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asm volatile ("movec %/cacr,%/d0\n\t"
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"oriw %0,%/d0\n\t"
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"movec %/d0,%/cacr"
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: : "i" (FLUSH_I_AND_D)
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: "d0");
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#ifdef CONFIG_M68K_L2_CACHE
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if(mach_l2_flush)
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mach_l2_flush(0);
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#endif
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}
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/*
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* cache_push() semantics: Write back any dirty cache data in the given area,
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* and invalidate the range in the instruction cache. It needs not (but may)
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* invalidate those entries also in the data cache. The range is defined by a
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* _physical_ address.
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*/
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void cache_push (unsigned long paddr, int len)
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{
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if (CPU_IS_040_OR_060) {
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int tmp = PAGE_SIZE;
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/*
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* on 68040 or 68060, push cache lines for pages in the range;
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* on the '040 this also invalidates the pushed lines, but not on
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* the '060!
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*/
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len += paddr & (PAGE_SIZE - 1);
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/*
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* Work around bug I17 in the 68060 affecting some instruction
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* lines not being invalidated properly.
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*/
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paddr &= PAGE_MASK;
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do {
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push040(paddr);
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paddr += tmp;
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} while ((len -= tmp) > 0);
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}
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/*
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* 68030/68020 have no writeback cache. On the other hand,
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* cache_push is actually a superset of cache_clear (the lines
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* get written back and invalidated), so we should make sure
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* to perform the corresponding actions. After all, this is getting
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* called in places where we've just loaded code, or whatever, so
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* flushing the icache is appropriate; flushing the dcache shouldn't
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* be required.
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*/
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else /* 68030 or 68020 */
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asm volatile ("movec %/cacr,%/d0\n\t"
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"oriw %0,%/d0\n\t"
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"movec %/d0,%/cacr"
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: : "i" (FLUSH_I)
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: "d0");
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#ifdef CONFIG_M68K_L2_CACHE
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if(mach_l2_flush)
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mach_l2_flush(1);
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#endif
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}
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static unsigned long virt_to_phys_slow(unsigned long vaddr)
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{
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if (CPU_IS_060) {
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mm_segment_t fs = get_fs();
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unsigned long paddr;
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set_fs(get_ds());
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/* The PLPAR instruction causes an access error if the translation
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* is not possible. To catch this we use the same exception mechanism
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* as for user space accesses in <asm/uaccess.h>. */
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asm volatile (".chip 68060\n"
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"1: plpar (%0)\n"
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".chip 68k\n"
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"2:\n"
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".section .fixup,\"ax\"\n"
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" .even\n"
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"3: sub.l %0,%0\n"
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" jra 2b\n"
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".previous\n"
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".section __ex_table,\"a\"\n"
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" .align 4\n"
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" .long 1b,3b\n"
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".previous"
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: "=a" (paddr)
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: "0" (vaddr));
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set_fs(fs);
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return paddr;
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} else if (CPU_IS_040) {
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mm_segment_t fs = get_fs();
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unsigned long mmusr;
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set_fs(get_ds());
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asm volatile (".chip 68040\n\t"
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"ptestr (%1)\n\t"
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"movec %%mmusr, %0\n\t"
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".chip 68k"
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: "=r" (mmusr)
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: "a" (vaddr));
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set_fs(fs);
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if (mmusr & MMU_R_040)
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return (mmusr & PAGE_MASK) | (vaddr & ~PAGE_MASK);
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} else {
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unsigned short mmusr;
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unsigned long *descaddr;
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asm volatile ("ptestr #5,%2@,#7,%0\n\t"
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"pmove %%psr,%1@"
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: "=a&" (descaddr)
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: "a" (&mmusr), "a" (vaddr));
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if (mmusr & (MMU_I|MMU_B|MMU_L))
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return 0;
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descaddr = phys_to_virt((unsigned long)descaddr);
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switch (mmusr & MMU_NUM) {
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case 1:
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return (*descaddr & 0xfe000000) | (vaddr & 0x01ffffff);
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case 2:
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return (*descaddr & 0xfffc0000) | (vaddr & 0x0003ffff);
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case 3:
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return (*descaddr & PAGE_MASK) | (vaddr & ~PAGE_MASK);
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}
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}
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return 0;
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}
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/* Push n pages at kernel virtual address and clear the icache */
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/* RZ: use cpush %bc instead of cpush %dc, cinv %ic */
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void flush_icache_range(unsigned long address, unsigned long endaddr)
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{
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if (CPU_IS_040_OR_060) {
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address &= PAGE_MASK;
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if (address >= PAGE_OFFSET && address < (unsigned long)high_memory) {
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do {
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asm volatile ("nop\n\t"
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".chip 68040\n\t"
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"cpushp %%bc,(%0)\n\t"
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".chip 68k"
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: : "a" (virt_to_phys((void *)address)));
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address += PAGE_SIZE;
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} while (address < endaddr);
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} else {
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do {
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asm volatile ("nop\n\t"
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".chip 68040\n\t"
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"cpushp %%bc,(%0)\n\t"
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".chip 68k"
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: : "a" (virt_to_phys_slow(address)));
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address += PAGE_SIZE;
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} while (address < endaddr);
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}
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} else {
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unsigned long tmp;
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asm volatile ("movec %%cacr,%0\n\t"
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"orw %1,%0\n\t"
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"movec %0,%%cacr"
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: "=&d" (tmp)
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: "di" (FLUSH_I));
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}
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}
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#ifndef CONFIG_SINGLE_MEMORY_CHUNK
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int mm_end_of_chunk (unsigned long addr, int len)
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{
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int i;
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for (i = 0; i < m68k_num_memory; i++)
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if (m68k_memory[i].addr + m68k_memory[i].size == addr + len)
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return 1;
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return 0;
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}
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#endif
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