Jianqun ee17eb83c4 clk: rockchip: fix rk3288 pll status register location ... In RK3288, APLL lock status bit is in GRF_SOC_STATUS1, but in RK3188, is GRFSOC_STATUS0. Signed-off-by: Jianqun <jay.xu@rock-chips.com> Also name the constant accordingly as GRF_SOC_STATUS1 to prevent confusion. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Doug Anderson <dianders@chromium.org> Tested-by: Doug Anderson <dianders@chromium.org>		2014-09-27 17:57:10 +02:00
..
clk-pll.c	clk: rockchip: change pll rate without a clk-notifier	2014-09-27 17:57:04 +02:00
clk-rk3188.c	clk: rockchip: fix rk3066 pll status register location	2014-09-27 17:57:07 +02:00
clk-rk3288.c	clk: rockchip: fix rk3288 pll status register location	2014-09-27 17:57:10 +02:00
clk-rockchip.c
clk.c	clk: rockchip: protect critical clocks from getting disabled	2014-09-02 15:03:18 -07:00
clk.h	clk: rockchip: protect critical clocks from getting disabled	2014-09-02 15:03:18 -07:00
Makefile	clk: rockchip: add clock controller for rk3288	2014-07-13 12:17:10 -07:00
softrst.c	clk: rockchip: add reset controller	2014-07-13 12:17:07 -07:00