cf293a4f0e
Replace HTTP links with HTTPS ones: SOFTLOGIC 6x10 MPEG CODEC Rationale: Reduces attack surface on kernel devs opening the links for MITM as HTTPS traffic is much harder to manipulate. Deterministic algorithm: For each file: If not .svg: For each line: If doesn't contain `\bxmlns\b`: If neither `\bgnu\.org/license`, nor `\bmozilla\.org/MPL\b`: If both the HTTP and HTTPS versions return 200 OK and serve the same content: Replace HTTP with HTTPS. Signed-off-by: Alexander A. Klimov <grandmaster@al2klimov.de> Signed-off-by: Ismael Luceno <ismael@iodev.co.uk> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
196 lines
4.6 KiB
C
196 lines
4.6 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2010-2013 Bluecherry, LLC <https://www.bluecherrydvr.com>
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*
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* Original author:
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* Ben Collins <bcollins@ubuntu.com>
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*
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* Additional work by:
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* John Brooks <john.brooks@bluecherry.net>
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*/
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#include <linux/kernel.h>
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#include <linux/fs.h>
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#include <linux/delay.h>
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#include <linux/uaccess.h>
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#include "solo6x10.h"
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static void solo_gpio_mode(struct solo_dev *solo_dev,
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unsigned int port_mask, unsigned int mode)
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{
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int port;
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unsigned int ret;
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ret = solo_reg_read(solo_dev, SOLO_GPIO_CONFIG_0);
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/* To set gpio */
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for (port = 0; port < 16; port++) {
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if (!((1 << port) & port_mask))
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continue;
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ret &= (~(3 << (port << 1)));
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ret |= ((mode & 3) << (port << 1));
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}
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solo_reg_write(solo_dev, SOLO_GPIO_CONFIG_0, ret);
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/* To set extended gpio - sensor */
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ret = solo_reg_read(solo_dev, SOLO_GPIO_CONFIG_1);
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for (port = 0; port < 16; port++) {
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if (!((1UL << (port + 16)) & port_mask))
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continue;
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if (!mode)
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ret &= ~(1UL << port);
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else
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ret |= 1UL << port;
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}
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/* Enable GPIO[31:16] */
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ret |= 0xffff0000;
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solo_reg_write(solo_dev, SOLO_GPIO_CONFIG_1, ret);
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}
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static void solo_gpio_set(struct solo_dev *solo_dev, unsigned int value)
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{
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solo_reg_write(solo_dev, SOLO_GPIO_DATA_OUT,
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solo_reg_read(solo_dev, SOLO_GPIO_DATA_OUT) | value);
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}
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static void solo_gpio_clear(struct solo_dev *solo_dev, unsigned int value)
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{
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solo_reg_write(solo_dev, SOLO_GPIO_DATA_OUT,
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solo_reg_read(solo_dev, SOLO_GPIO_DATA_OUT) & ~value);
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}
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static void solo_gpio_config(struct solo_dev *solo_dev)
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{
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/* Video reset */
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solo_gpio_mode(solo_dev, 0x30, 1);
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solo_gpio_clear(solo_dev, 0x30);
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udelay(100);
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solo_gpio_set(solo_dev, 0x30);
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udelay(100);
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/* Warning: Don't touch the next line unless you're sure of what
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* you're doing: first four gpio [0-3] are used for video. */
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solo_gpio_mode(solo_dev, 0x0f, 2);
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/* We use bit 8-15 of SOLO_GPIO_CONFIG_0 for relay purposes */
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solo_gpio_mode(solo_dev, 0xff00, 1);
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/* Initially set relay status to 0 */
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solo_gpio_clear(solo_dev, 0xff00);
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/* Set input pins direction */
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solo_gpio_mode(solo_dev, 0xffff0000, 0);
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}
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#ifdef CONFIG_GPIOLIB
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/* Pins 0-7 are not exported, because it seems from code above they are
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* used for internal purposes. So offset 0 corresponds to pin 8, therefore
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* offsets 0-7 are relay GPIOs, 8-23 - input GPIOs.
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*/
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static int solo_gpiochip_get_direction(struct gpio_chip *chip,
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unsigned int offset)
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{
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int ret, mode;
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struct solo_dev *solo_dev = gpiochip_get_data(chip);
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if (offset < 8) {
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ret = solo_reg_read(solo_dev, SOLO_GPIO_CONFIG_0);
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mode = 3 & (ret >> ((offset + 8) * 2));
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} else {
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ret = solo_reg_read(solo_dev, SOLO_GPIO_CONFIG_1);
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mode = 1 & (ret >> (offset - 8));
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}
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if (!mode)
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return 1;
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else if (mode == 1)
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return 0;
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return -1;
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}
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static int solo_gpiochip_direction_input(struct gpio_chip *chip,
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unsigned int offset)
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{
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return -1;
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}
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static int solo_gpiochip_direction_output(struct gpio_chip *chip,
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unsigned int offset, int value)
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{
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return -1;
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}
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static int solo_gpiochip_get(struct gpio_chip *chip,
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unsigned int offset)
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{
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int ret;
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struct solo_dev *solo_dev = gpiochip_get_data(chip);
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ret = solo_reg_read(solo_dev, SOLO_GPIO_DATA_IN);
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return 1 & (ret >> (offset + 8));
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}
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static void solo_gpiochip_set(struct gpio_chip *chip,
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unsigned int offset, int value)
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{
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struct solo_dev *solo_dev = gpiochip_get_data(chip);
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if (value)
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solo_gpio_set(solo_dev, 1 << (offset + 8));
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else
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solo_gpio_clear(solo_dev, 1 << (offset + 8));
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}
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#endif
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int solo_gpio_init(struct solo_dev *solo_dev)
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{
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#ifdef CONFIG_GPIOLIB
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int ret;
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#endif
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solo_gpio_config(solo_dev);
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#ifdef CONFIG_GPIOLIB
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solo_dev->gpio_dev.label = SOLO6X10_NAME"_gpio";
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solo_dev->gpio_dev.parent = &solo_dev->pdev->dev;
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solo_dev->gpio_dev.owner = THIS_MODULE;
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solo_dev->gpio_dev.base = -1;
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solo_dev->gpio_dev.ngpio = 24;
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solo_dev->gpio_dev.can_sleep = 0;
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solo_dev->gpio_dev.get_direction = solo_gpiochip_get_direction;
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solo_dev->gpio_dev.direction_input = solo_gpiochip_direction_input;
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solo_dev->gpio_dev.direction_output = solo_gpiochip_direction_output;
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solo_dev->gpio_dev.get = solo_gpiochip_get;
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solo_dev->gpio_dev.set = solo_gpiochip_set;
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ret = gpiochip_add_data(&solo_dev->gpio_dev, solo_dev);
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if (ret) {
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solo_dev->gpio_dev.label = NULL;
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return -1;
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}
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#endif
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return 0;
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}
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void solo_gpio_exit(struct solo_dev *solo_dev)
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{
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#ifdef CONFIG_GPIOLIB
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if (solo_dev->gpio_dev.label) {
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gpiochip_remove(&solo_dev->gpio_dev);
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solo_dev->gpio_dev.label = NULL;
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}
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#endif
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solo_gpio_clear(solo_dev, 0x30);
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solo_gpio_config(solo_dev);
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}
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