7605b39061
In the the sequence:
ei
..
mfc0 $x, $status
the mfc0 may not see the SR_IE bit set. This was a deliberate bug in the
kernel code because we knew this was a safe thing to do on all R2 silicon
so far but new silicon is changing this.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
182 lines
3.7 KiB
C
182 lines
3.7 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2003, 2004 Ralf Baechle <ralf@linux-mips.org>
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* Copyright (C) MIPS Technologies, Inc.
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* written by Ralf Baechle <ralf@linux-mips.org>
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*/
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#ifndef _ASM_HAZARDS_H
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#define _ASM_HAZARDS_H
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#ifdef __ASSEMBLY__
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#define ASMMACRO(name, code...) .macro name; code; .endm
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#else
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#define ASMMACRO(name, code...) \
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__asm__(".macro " #name "; " #code "; .endm"); \
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\
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static inline void name(void) \
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{ \
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__asm__ __volatile__ (#name); \
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}
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#endif
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ASMMACRO(_ssnop,
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sll $0, $0, 1
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)
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ASMMACRO(_ehb,
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sll $0, $0, 3
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)
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/*
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* TLB hazards
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*/
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#if defined(CONFIG_CPU_MIPSR2)
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/*
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* MIPSR2 defines ehb for hazard avoidance
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*/
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ASMMACRO(mtc0_tlbw_hazard,
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_ehb
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)
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ASMMACRO(tlbw_use_hazard,
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_ehb
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)
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ASMMACRO(tlb_probe_hazard,
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_ehb
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)
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ASMMACRO(irq_enable_hazard,
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_ehb
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)
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ASMMACRO(irq_disable_hazard,
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_ehb
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)
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ASMMACRO(back_to_back_c0_hazard,
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_ehb
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)
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/*
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* gcc has a tradition of misscompiling the previous construct using the
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* address of a label as argument to inline assembler. Gas otoh has the
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* annoying difference between la and dla which are only usable for 32-bit
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* rsp. 64-bit code, so can't be used without conditional compilation.
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* The alterantive is switching the assembler to 64-bit code which happens
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* to work right even for 32-bit code ...
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*/
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#define instruction_hazard() \
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do { \
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unsigned long tmp; \
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\
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__asm__ __volatile__( \
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" .set mips64r2 \n" \
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" dla %0, 1f \n" \
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" jr.hb %0 \n" \
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" .set mips0 \n" \
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"1: \n" \
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: "=r" (tmp)); \
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} while (0)
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#elif defined(CONFIG_CPU_R10000)
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/*
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* R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
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*/
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ASMMACRO(mtc0_tlbw_hazard,
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)
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ASMMACRO(tlbw_use_hazard,
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)
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ASMMACRO(tlb_probe_hazard,
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)
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ASMMACRO(irq_enable_hazard,
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)
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ASMMACRO(irq_disable_hazard,
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)
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ASMMACRO(back_to_back_c0_hazard,
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)
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#define instruction_hazard() do { } while (0)
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#elif defined(CONFIG_CPU_RM9000)
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/*
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* RM9000 hazards. When the JTLB is updated by tlbwi or tlbwr, a subsequent
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* use of the JTLB for instructions should not occur for 4 cpu cycles and use
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* for data translations should not occur for 3 cpu cycles.
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*/
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ASMMACRO(mtc0_tlbw_hazard,
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_ssnop; _ssnop; _ssnop; _ssnop
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)
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ASMMACRO(tlbw_use_hazard,
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_ssnop; _ssnop; _ssnop; _ssnop
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)
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ASMMACRO(tlb_probe_hazard,
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_ssnop; _ssnop; _ssnop; _ssnop
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)
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ASMMACRO(irq_enable_hazard,
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)
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ASMMACRO(irq_disable_hazard,
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)
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ASMMACRO(back_to_back_c0_hazard,
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)
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#define instruction_hazard() do { } while (0)
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#elif defined(CONFIG_CPU_SB1)
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/*
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* Mostly like R4000 for historic reasons
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*/
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ASMMACRO(mtc0_tlbw_hazard,
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)
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ASMMACRO(tlbw_use_hazard,
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)
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ASMMACRO(tlb_probe_hazard,
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)
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ASMMACRO(irq_enable_hazard,
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)
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ASMMACRO(irq_disable_hazard,
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_ssnop; _ssnop; _ssnop
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)
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ASMMACRO(back_to_back_c0_hazard,
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)
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#define instruction_hazard() do { } while (0)
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#else
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/*
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* Finally the catchall case for all other processors including R4000, R4400,
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* R4600, R4700, R5000, RM7000, NEC VR41xx etc.
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*
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* The taken branch will result in a two cycle penalty for the two killed
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* instructions on R4000 / R4400. Other processors only have a single cycle
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* hazard so this is nice trick to have an optimal code for a range of
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* processors.
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*/
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ASMMACRO(mtc0_tlbw_hazard,
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nop; nop
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)
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ASMMACRO(tlbw_use_hazard,
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nop; nop; nop
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)
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ASMMACRO(tlb_probe_hazard,
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nop; nop; nop
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)
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ASMMACRO(irq_enable_hazard,
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)
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ASMMACRO(irq_disable_hazard,
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nop; nop; nop
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)
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ASMMACRO(back_to_back_c0_hazard,
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_ssnop; _ssnop; _ssnop;
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)
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#define instruction_hazard() do { } while (0)
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#endif
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#endif /* _ASM_HAZARDS_H */
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