6378c02531
Checkpatch compliance The latest version of checkpatch found the following style errors in the code Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
404 lines
15 KiB
C
404 lines
15 KiB
C
/* bnx2x_fw_defs.h: Broadcom Everest network driver.
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*
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* Copyright (c) 2007-2008 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation.
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*/
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#define CSTORM_ASSERT_LIST_INDEX_OFFSET \
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(IS_E1H_OFFSET ? 0x7000 : 0x1000)
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#define CSTORM_ASSERT_LIST_OFFSET(idx) \
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(IS_E1H_OFFSET ? (0x7020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
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#define CSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
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(IS_E1H_OFFSET ? (0x8522 + ((function>>1) * 0x40) + \
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((function&1) * 0x100) + (index * 0x4)) : (0x1922 + (function * \
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0x40) + (index * 0x4)))
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#define CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
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(IS_E1H_OFFSET ? (0x8500 + ((function>>1) * 0x40) + \
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((function&1) * 0x100)) : (0x1900 + (function * 0x40)))
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#define CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
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(IS_E1H_OFFSET ? (0x8508 + ((function>>1) * 0x40) + \
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((function&1) * 0x100)) : (0x1908 + (function * 0x40)))
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#define CSTORM_FUNCTION_MODE_OFFSET \
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(IS_E1H_OFFSET ? 0x11e8 : 0xffffffff)
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#define CSTORM_HC_BTR_OFFSET(port) \
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(IS_E1H_OFFSET ? (0x8704 + (port * 0xf0)) : (0x1984 + (port * 0xc0)))
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#define CSTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index) \
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(IS_E1H_OFFSET ? (0x801a + (port * 0x280) + (cpu_id * 0x28) + \
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(index * 0x4)) : (0x141a + (port * 0x280) + (cpu_id * 0x28) + \
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(index * 0x4)))
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#define CSTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index) \
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(IS_E1H_OFFSET ? (0x8018 + (port * 0x280) + (cpu_id * 0x28) + \
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(index * 0x4)) : (0x1418 + (port * 0x280) + (cpu_id * 0x28) + \
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(index * 0x4)))
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#define CSTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id) \
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(IS_E1H_OFFSET ? (0x8000 + (port * 0x280) + (cpu_id * 0x28)) : \
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(0x1400 + (port * 0x280) + (cpu_id * 0x28)))
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#define CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, cpu_id) \
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(IS_E1H_OFFSET ? (0x8008 + (port * 0x280) + (cpu_id * 0x28)) : \
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(0x1408 + (port * 0x280) + (cpu_id * 0x28)))
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#define CSTORM_STATS_FLAGS_OFFSET(function) \
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(IS_E1H_OFFSET ? (0x1108 + (function * 0x8)) : (0x5108 + \
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(function * 0x8)))
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#define TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(function) \
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(IS_E1H_OFFSET ? (0x31c0 + (function * 0x20)) : 0xffffffff)
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#define TSTORM_ASSERT_LIST_INDEX_OFFSET \
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(IS_E1H_OFFSET ? 0xa000 : 0x1000)
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#define TSTORM_ASSERT_LIST_OFFSET(idx) \
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(IS_E1H_OFFSET ? (0xa020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
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#define TSTORM_CLIENT_CONFIG_OFFSET(port, client_id) \
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(IS_E1H_OFFSET ? (0x3358 + (port * 0x3e8) + (client_id * 0x28)) \
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: (0x9c8 + (port * 0x2f8) + (client_id * 0x28)))
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#define TSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
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(IS_E1H_OFFSET ? (0xb01a + ((function>>1) * 0x28) + \
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((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \
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0x28) + (index * 0x4)))
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#define TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
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(IS_E1H_OFFSET ? (0xb000 + ((function>>1) * 0x28) + \
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((function&1) * 0xa0)) : (0x1400 + (function * 0x28)))
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#define TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
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(IS_E1H_OFFSET ? (0xb008 + ((function>>1) * 0x28) + \
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((function&1) * 0xa0)) : (0x1408 + (function * 0x28)))
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#define TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \
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(IS_E1H_OFFSET ? (0x2b80 + (function * 0x8)) : (0x4b68 + \
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(function * 0x8)))
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#define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(function) \
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(IS_E1H_OFFSET ? (0x3000 + (function * 0x38)) : (0x1500 + \
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(function * 0x38)))
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#define TSTORM_FUNCTION_MODE_OFFSET \
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(IS_E1H_OFFSET ? 0x1ad0 : 0xffffffff)
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#define TSTORM_HC_BTR_OFFSET(port) \
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(IS_E1H_OFFSET ? (0xb144 + (port * 0x30)) : (0x1454 + (port * 0x18)))
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#define TSTORM_INDIRECTION_TABLE_OFFSET(function) \
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(IS_E1H_OFFSET ? (0x12c8 + (function * 0x80)) : (0x22c8 + \
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(function * 0x80)))
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#define TSTORM_INDIRECTION_TABLE_SIZE 0x80
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#define TSTORM_MAC_FILTER_CONFIG_OFFSET(function) \
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(IS_E1H_OFFSET ? (0x3008 + (function * 0x38)) : (0x1508 + \
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(function * 0x38)))
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#define TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \
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(IS_E1H_OFFSET ? (0x2010 + (port * 0x5b0) + (stats_counter_id * \
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0x50)) : (0x4000 + (port * 0x3f0) + (stats_counter_id * 0x38)))
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#define TSTORM_RX_PRODS_OFFSET(port, client_id) \
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(IS_E1H_OFFSET ? (0x3350 + (port * 0x3e8) + (client_id * 0x28)) \
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: (0x9c0 + (port * 0x2f8) + (client_id * 0x28)))
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#define TSTORM_STATS_FLAGS_OFFSET(function) \
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(IS_E1H_OFFSET ? (0x2c00 + (function * 0x8)) : (0x4b88 + \
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(function * 0x8)))
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#define TSTORM_TPA_EXIST_OFFSET (IS_E1H_OFFSET ? 0x3b30 : 0x1c20)
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#define USTORM_AGG_DATA_OFFSET (IS_E1H_OFFSET ? 0xa040 : 0x2c10)
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#define USTORM_AGG_DATA_SIZE (IS_E1H_OFFSET ? 0x2440 : 0x1200)
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#define USTORM_ASSERT_LIST_INDEX_OFFSET \
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(IS_E1H_OFFSET ? 0x8000 : 0x1000)
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#define USTORM_ASSERT_LIST_OFFSET(idx) \
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(IS_E1H_OFFSET ? (0x8020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
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#define USTORM_CQE_PAGE_BASE_OFFSET(port, clientId) \
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(IS_E1H_OFFSET ? (0x3298 + (port * 0x258) + (clientId * 0x18)) : \
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(0x5450 + (port * 0x1c8) + (clientId * 0x18)))
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#define USTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
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(IS_E1H_OFFSET ? (0x951a + ((function>>1) * 0x28) + \
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((function&1) * 0xa0) + (index * 0x4)) : (0x191a + (function * \
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0x28) + (index * 0x4)))
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#define USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
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(IS_E1H_OFFSET ? (0x9500 + ((function>>1) * 0x28) + \
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((function&1) * 0xa0)) : (0x1900 + (function * 0x28)))
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#define USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
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(IS_E1H_OFFSET ? (0x9508 + ((function>>1) * 0x28) + \
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((function&1) * 0xa0)) : (0x1908 + (function * 0x28)))
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#define USTORM_FUNCTION_MODE_OFFSET \
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(IS_E1H_OFFSET ? 0x2448 : 0xffffffff)
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#define USTORM_HC_BTR_OFFSET(port) \
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(IS_E1H_OFFSET ? (0x9644 + (port * 0xd0)) : (0x1954 + (port * 0xb8)))
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#define USTORM_MAX_AGG_SIZE_OFFSET(port, clientId) \
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(IS_E1H_OFFSET ? (0x3290 + (port * 0x258) + (clientId * 0x18)) : \
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(0x5448 + (port * 0x1c8) + (clientId * 0x18)))
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#define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(function) \
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(IS_E1H_OFFSET ? (0x2408 + (function * 0x8)) : (0x5408 + \
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(function * 0x8)))
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#define USTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index) \
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(IS_E1H_OFFSET ? (0x901a + (port * 0x280) + (cpu_id * 0x28) + \
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(index * 0x4)) : (0x141a + (port * 0x280) + (cpu_id * 0x28) + \
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(index * 0x4)))
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#define USTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index) \
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(IS_E1H_OFFSET ? (0x9018 + (port * 0x280) + (cpu_id * 0x28) + \
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(index * 0x4)) : (0x1418 + (port * 0x280) + (cpu_id * 0x28) + \
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(index * 0x4)))
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#define USTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id) \
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(IS_E1H_OFFSET ? (0x9000 + (port * 0x280) + (cpu_id * 0x28)) : \
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(0x1400 + (port * 0x280) + (cpu_id * 0x28)))
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#define USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, cpu_id) \
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(IS_E1H_OFFSET ? (0x9008 + (port * 0x280) + (cpu_id * 0x28)) : \
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(0x1408 + (port * 0x280) + (cpu_id * 0x28)))
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#define XSTORM_ASSERT_LIST_INDEX_OFFSET \
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(IS_E1H_OFFSET ? 0x9000 : 0x1000)
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#define XSTORM_ASSERT_LIST_OFFSET(idx) \
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(IS_E1H_OFFSET ? (0x9020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
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#define XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) \
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(IS_E1H_OFFSET ? (0x24a8 + (port * 0x40)) : (0x3ba0 + (port * 0x40)))
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#define XSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
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(IS_E1H_OFFSET ? (0xa01a + ((function>>1) * 0x28) + \
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((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \
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0x28) + (index * 0x4)))
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#define XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
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(IS_E1H_OFFSET ? (0xa000 + ((function>>1) * 0x28) + \
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((function&1) * 0xa0)) : (0x1400 + (function * 0x28)))
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#define XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
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(IS_E1H_OFFSET ? (0xa008 + ((function>>1) * 0x28) + \
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((function&1) * 0xa0)) : (0x1408 + (function * 0x28)))
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#define XSTORM_E1HOV_OFFSET(function) \
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(IS_E1H_OFFSET ? (0x2ab8 + (function * 0x2)) : 0xffffffff)
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#define XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \
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(IS_E1H_OFFSET ? (0x2418 + (function * 0x8)) : (0x3b70 + \
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(function * 0x8)))
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#define XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(function) \
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(IS_E1H_OFFSET ? (0x2568 + (function * 0x70)) : (0x3c60 + \
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(function * 0x70)))
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#define XSTORM_FUNCTION_MODE_OFFSET \
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(IS_E1H_OFFSET ? 0x2ac8 : 0xffffffff)
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#define XSTORM_HC_BTR_OFFSET(port) \
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(IS_E1H_OFFSET ? (0xa144 + (port * 0x30)) : (0x1454 + (port * 0x18)))
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#define XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \
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(IS_E1H_OFFSET ? (0xc000 + (port * 0x3f0) + (stats_counter_id * \
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0x38)) : (0x3378 + (port * 0x3f0) + (stats_counter_id * 0x38)))
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#define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(function) \
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(IS_E1H_OFFSET ? (0x2528 + (function * 0x70)) : (0x3c20 + \
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(function * 0x70)))
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#define XSTORM_SPQ_PAGE_BASE_OFFSET(function) \
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(IS_E1H_OFFSET ? (0x2000 + (function * 0x10)) : (0x3328 + \
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(function * 0x10)))
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#define XSTORM_SPQ_PROD_OFFSET(function) \
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(IS_E1H_OFFSET ? (0x2008 + (function * 0x10)) : (0x3330 + \
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(function * 0x10)))
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#define XSTORM_STATS_FLAGS_OFFSET(function) \
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(IS_E1H_OFFSET ? (0x23d8 + (function * 0x8)) : (0x3b60 + \
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(function * 0x8)))
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#define COMMON_ASM_INVALID_ASSERT_OPCODE 0x0
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/**
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* This file defines HSI constatnts for the ETH flow
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*/
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#ifdef _EVEREST_MICROCODE
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#include "microcode_constants.h"
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#include "eth_rx_bd.h"
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#include "eth_tx_bd.h"
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#include "eth_rx_cqe.h"
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#include "eth_rx_sge.h"
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#include "eth_rx_cqe_next_page.h"
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#endif
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/* RSS hash types */
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#define DEFAULT_HASH_TYPE 0
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#define IPV4_HASH_TYPE 1
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#define TCP_IPV4_HASH_TYPE 2
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#define IPV6_HASH_TYPE 3
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#define TCP_IPV6_HASH_TYPE 4
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/* Ethernet Ring parmaters */
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#define X_ETH_LOCAL_RING_SIZE 13
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#define FIRST_BD_IN_PKT 0
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#define PARSE_BD_INDEX 1
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#define NUM_OF_ETH_BDS_IN_PAGE \
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((PAGE_SIZE) / (STRUCT_SIZE(eth_tx_bd)/8))
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/* Rx ring params */
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#define U_ETH_LOCAL_BD_RING_SIZE (16)
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#define U_ETH_LOCAL_SGE_RING_SIZE (12)
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#define U_ETH_SGL_SIZE (8)
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#define U_ETH_BDS_PER_PAGE_MASK \
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((PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8))-1)
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#define U_ETH_CQE_PER_PAGE_MASK \
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((PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe)/8))-1)
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#define U_ETH_SGES_PER_PAGE_MASK \
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((PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8))-1)
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#define U_ETH_SGES_PER_PAGE_INVERSE_MASK \
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(0xFFFF - ((PAGE_SIZE/((STRUCT_SIZE(eth_rx_sge))/8))-1))
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#define TU_ETH_CQES_PER_PAGE \
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(PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe_next_page)/8))
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#define U_ETH_BDS_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8))
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#define U_ETH_SGES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8))
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#define U_ETH_UNDEFINED_Q 0xFF
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/* values of command IDs in the ramrod message */
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#define RAMROD_CMD_ID_ETH_PORT_SETUP (80)
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#define RAMROD_CMD_ID_ETH_CLIENT_SETUP (85)
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#define RAMROD_CMD_ID_ETH_STAT_QUERY (90)
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#define RAMROD_CMD_ID_ETH_UPDATE (100)
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#define RAMROD_CMD_ID_ETH_HALT (105)
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#define RAMROD_CMD_ID_ETH_SET_MAC (110)
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#define RAMROD_CMD_ID_ETH_CFC_DEL (115)
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#define RAMROD_CMD_ID_ETH_PORT_DEL (120)
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#define RAMROD_CMD_ID_ETH_FORWARD_SETUP (125)
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/* command values for set mac command */
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#define T_ETH_MAC_COMMAND_SET 0
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#define T_ETH_MAC_COMMAND_INVALIDATE 1
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#define T_ETH_INDIRECTION_TABLE_SIZE 128
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/*The CRC32 seed, that is used for the hash(reduction) multicast address */
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#define T_ETH_CRC32_HASH_SEED 0x00000000
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/* Maximal L2 clients supported */
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#define ETH_MAX_RX_CLIENTS_E1 19
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#define ETH_MAX_RX_CLIENTS_E1H 25
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/* Maximal aggregation queues supported */
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#define ETH_MAX_AGGREGATION_QUEUES_E1 (32)
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#define ETH_MAX_AGGREGATION_QUEUES_E1H (64)
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/**
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* This file defines HSI constatnts common to all microcode flows
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*/
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/* Connection types */
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#define ETH_CONNECTION_TYPE 0
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#define TOE_CONNECTION_TYPE 1
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#define RDMA_CONNECTION_TYPE 2
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#define ISCSI_CONNECTION_TYPE 3
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#define FCOE_CONNECTION_TYPE 4
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#define RESERVED_CONNECTION_TYPE_0 5
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#define RESERVED_CONNECTION_TYPE_1 6
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#define RESERVED_CONNECTION_TYPE_2 7
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#define PROTOCOL_STATE_BIT_OFFSET 6
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#define ETH_STATE (ETH_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
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#define TOE_STATE (TOE_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
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#define RDMA_STATE (RDMA_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
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#define ISCSI_STATE \
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(ISCSI_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
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#define FCOE_STATE (FCOE_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
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/* microcode fixed page page size 4K (chains and ring segments) */
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#define MC_PAGE_SIZE (4096)
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/* Host coalescing constants */
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/* index numbers */
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#define HC_USTORM_DEF_SB_NUM_INDICES 4
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#define HC_CSTORM_DEF_SB_NUM_INDICES 8
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#define HC_XSTORM_DEF_SB_NUM_INDICES 4
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#define HC_TSTORM_DEF_SB_NUM_INDICES 4
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#define HC_USTORM_SB_NUM_INDICES 4
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#define HC_CSTORM_SB_NUM_INDICES 4
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/* index values - which counterto update */
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#define HC_INDEX_U_TOE_RX_CQ_CONS 0
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#define HC_INDEX_U_ETH_RX_CQ_CONS 1
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#define HC_INDEX_U_ETH_RX_BD_CONS 2
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#define HC_INDEX_U_FCOE_EQ_CONS 3
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#define HC_INDEX_C_TOE_TX_CQ_CONS 0
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#define HC_INDEX_C_ETH_TX_CQ_CONS 1
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#define HC_INDEX_C_ISCSI_EQ_CONS 2
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#define HC_INDEX_DEF_X_SPQ_CONS 0
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#define HC_INDEX_DEF_C_RDMA_EQ_CONS 0
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#define HC_INDEX_DEF_C_RDMA_NAL_PROD 1
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#define HC_INDEX_DEF_C_ETH_FW_TX_CQ_CONS 2
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#define HC_INDEX_DEF_C_ETH_SLOW_PATH 3
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#define HC_INDEX_DEF_C_ETH_RDMA_CQ_CONS 4
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#define HC_INDEX_DEF_C_ETH_ISCSI_CQ_CONS 5
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#define HC_INDEX_DEF_U_ETH_RDMA_RX_CQ_CONS 0
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#define HC_INDEX_DEF_U_ETH_ISCSI_RX_CQ_CONS 1
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#define HC_INDEX_DEF_U_ETH_RDMA_RX_BD_CONS 2
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#define HC_INDEX_DEF_U_ETH_ISCSI_RX_BD_CONS 3
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/* used by the driver to get the SB offset */
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#define USTORM_ID 0
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#define CSTORM_ID 1
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#define XSTORM_ID 2
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#define TSTORM_ID 3
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#define ATTENTION_ID 4
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/* max number of slow path commands per port */
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#define MAX_RAMRODS_PER_PORT (8)
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/* values for RX ETH CQE type field */
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#define RX_ETH_CQE_TYPE_ETH_FASTPATH (0)
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#define RX_ETH_CQE_TYPE_ETH_RAMROD (1)
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/**** DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/
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#define EMULATION_FREQUENCY_FACTOR (1600)
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#define FPGA_FREQUENCY_FACTOR (100)
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#define TIMERS_TICK_SIZE_CHIP (1e-3)
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#define TIMERS_TICK_SIZE_EMUL \
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((TIMERS_TICK_SIZE_CHIP)/((EMULATION_FREQUENCY_FACTOR)))
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#define TIMERS_TICK_SIZE_FPGA \
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((TIMERS_TICK_SIZE_CHIP)/((FPGA_FREQUENCY_FACTOR)))
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#define TSEMI_CLK1_RESUL_CHIP (1e-3)
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#define TSEMI_CLK1_RESUL_EMUL \
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((TSEMI_CLK1_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
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#define TSEMI_CLK1_RESUL_FPGA \
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((TSEMI_CLK1_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
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#define USEMI_CLK1_RESUL_CHIP \
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(TIMERS_TICK_SIZE_CHIP)
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#define USEMI_CLK1_RESUL_EMUL \
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(TIMERS_TICK_SIZE_EMUL)
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#define USEMI_CLK1_RESUL_FPGA \
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(TIMERS_TICK_SIZE_FPGA)
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#define XSEMI_CLK1_RESUL_CHIP (1e-3)
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#define XSEMI_CLK1_RESUL_EMUL \
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((XSEMI_CLK1_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
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#define XSEMI_CLK1_RESUL_FPGA \
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((XSEMI_CLK1_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
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#define XSEMI_CLK2_RESUL_CHIP (1e-6)
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#define XSEMI_CLK2_RESUL_EMUL \
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((XSEMI_CLK2_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
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#define XSEMI_CLK2_RESUL_FPGA \
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((XSEMI_CLK2_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
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#define SDM_TIMER_TICK_RESUL_CHIP (4*(1e-6))
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#define SDM_TIMER_TICK_RESUL_EMUL \
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((SDM_TIMER_TICK_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
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#define SDM_TIMER_TICK_RESUL_FPGA \
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((SDM_TIMER_TICK_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
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/**** END DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/
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#define XSTORM_IP_ID_ROLL_HALF 0x8000
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#define XSTORM_IP_ID_ROLL_ALL 0
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#define FW_LOG_LIST_SIZE (50)
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#define NUM_OF_PROTOCOLS 4
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#define MAX_COS_NUMBER 16
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#define MAX_T_STAT_COUNTER_ID 18
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#define MAX_X_STAT_COUNTER_ID 18
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#define UNKNOWN_ADDRESS 0
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#define UNICAST_ADDRESS 1
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#define MULTICAST_ADDRESS 2
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#define BROADCAST_ADDRESS 3
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#define SINGLE_FUNCTION 0
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#define MULTI_FUNCTION 1
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#define IP_V4 0
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#define IP_V6 1
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