7f386ac327
Create general kernel debugger cache flushing for MN10300 and get rid of the old stuff that gdbstub was using. Signed-off-by: David Howells <dhowells@redhat.com>
115 lines
3.2 KiB
ArmAsm
115 lines
3.2 KiB
ArmAsm
/* MN10300 CPU cache invalidation routines, using direct tag flushing
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*
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* Copyright (C) 2011 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public Licence
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* as published by the Free Software Foundation; either version
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* 2 of the Licence, or (at your option) any later version.
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*/
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#include <linux/sys.h>
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#include <linux/linkage.h>
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#include <asm/smp.h>
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#include <asm/page.h>
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#include <asm/cache.h>
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#include <asm/irqflags.h>
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#include <asm/cacheflush.h>
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#include "cache.inc"
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.am33_2
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###############################################################################
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#
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# void debugger_local_cache_flushinv(void)
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#
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# Flush the entire data cache back to RAM and invalidate the icache
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#
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###############################################################################
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ALIGN
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.globl debugger_local_cache_flushinv
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.type debugger_local_cache_flushinv,@function
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debugger_local_cache_flushinv:
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#
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# firstly flush the dcache
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#
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movhu (CHCTR),d0
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btst CHCTR_DCEN|CHCTR_ICEN,d0
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beq debugger_local_cache_flushinv_end
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btst CHCTR_DCEN,d0
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beq debugger_local_cache_flushinv_no_dcache
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# read the addresses tagged in the cache's tag RAM and attempt to flush
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# those addresses specifically
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# - we rely on the hardware to filter out invalid tag entry addresses
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mov DCACHE_TAG(0,0),a0 # dcache tag RAM access address
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mov DCACHE_PURGE(0,0),a1 # dcache purge request address
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mov L1_CACHE_NWAYS*L1_CACHE_NENTRIES,e0 # total number of entries
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mn10300_local_dcache_flush_loop:
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mov (a0),d0
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and L1_CACHE_TAG_MASK,d0
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or L1_CACHE_TAG_VALID,d0 # retain valid entries in the
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# cache
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mov d0,(a1) # conditional purge
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add L1_CACHE_BYTES,a0
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add L1_CACHE_BYTES,a1
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add -1,e0
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bne mn10300_local_dcache_flush_loop
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debugger_local_cache_flushinv_no_dcache:
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#
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# secondly, invalidate the icache if it is enabled
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#
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mov CHCTR,a0
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movhu (a0),d0
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btst CHCTR_ICEN,d0
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beq debugger_local_cache_flushinv_end
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invalidate_icache 1
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debugger_local_cache_flushinv_end:
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ret [],0
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.size debugger_local_cache_flushinv,.-debugger_local_cache_flushinv
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###############################################################################
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#
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# void debugger_local_cache_flushinv_one(u8 *addr)
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#
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# Invalidate one particular cacheline if it's in the icache
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#
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###############################################################################
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ALIGN
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.globl debugger_local_cache_flushinv_one
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.type debugger_local_cache_flushinv_one,@function
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debugger_local_cache_flushinv_one:
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movhu (CHCTR),d1
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btst CHCTR_DCEN|CHCTR_ICEN,d1
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beq debugger_local_cache_flushinv_one_end
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btst CHCTR_DCEN,d1
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beq debugger_local_cache_flushinv_one_icache
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# round cacheline addr down
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and L1_CACHE_TAG_MASK,d0
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mov d0,a1
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# determine the dcache purge control reg address
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mov DCACHE_PURGE(0,0),a0
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and L1_CACHE_TAG_ENTRY,d0
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add d0,a0
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# retain valid entries in the cache
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or L1_CACHE_TAG_VALID,a1
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# conditionally purge this line in all ways
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mov a1,(L1_CACHE_WAYDISP*0,a0)
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# now go and do the icache
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bra debugger_local_cache_flushinv_one_icache
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debugger_local_cache_flushinv_one_end:
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ret [],0
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.size debugger_local_cache_flushinv_one,.-debugger_local_cache_flushinv_one
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