e7cc9a7340
The idea is that we want to get rid of the in/out/readb/writeb callbacks from the machvec and replace that with simple inline read and write operations to memory. Fast and simple for most hardware devices (think pci). Some devices require special treatment though - like 16-bit only CF devices - so we need to have some method to hook in callbacks. This patch makes it possible to add a per-device trap generating filter. This way we can get maximum performance of sane hardware - which doesn't need this filter - and crappy hardware works but gets punished by a performance hit. V2 changes things around a bit and replaces io access callbacks with a simple minimum_bus_width value. In the future we can add stride as well. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
365 lines
11 KiB
C
365 lines
11 KiB
C
#ifndef __ASM_SH_IO_H
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#define __ASM_SH_IO_H
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/*
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* Convention:
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* read{b,w,l}/write{b,w,l} are for PCI,
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* while in{b,w,l}/out{b,w,l} are for ISA
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* These may (will) be platform specific function.
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* In addition we have 'pausing' versions: in{b,w,l}_p/out{b,w,l}_p
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* and 'string' versions: ins{b,w,l}/outs{b,w,l}
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* For read{b,w,l} and write{b,w,l} there are also __raw versions, which
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* do not have a memory barrier after them.
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*
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* In addition, we have
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* ctrl_in{b,w,l}/ctrl_out{b,w,l} for SuperH specific I/O.
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* which are processor specific.
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*/
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/*
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* We follow the Alpha convention here:
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* __inb expands to an inline function call (which calls via the mv)
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* _inb is a real function call (note ___raw fns are _ version of __raw)
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* inb by default expands to _inb, but the machine specific code may
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* define it to __inb if it chooses.
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*/
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#include <asm/cache.h>
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#include <asm/system.h>
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#include <asm/addrspace.h>
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#include <asm/machvec.h>
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#include <asm/pgtable.h>
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#include <asm-generic/iomap.h>
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#ifdef __KERNEL__
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/*
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* Depending on which platform we are running on, we need different
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* I/O functions.
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*/
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#define __IO_PREFIX generic
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#include <asm/io_generic.h>
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#include <asm/io_trapped.h>
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#define maybebadio(port) \
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printk(KERN_ERR "bad PC-like io %s:%u for port 0x%lx at 0x%08x\n", \
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__FUNCTION__, __LINE__, (port), (u32)__builtin_return_address(0))
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/*
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* Since boards are able to define their own set of I/O routines through
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* their respective machine vector, we always wrap through the mv.
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*
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* Also, in the event that a board hasn't provided its own definition for
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* a given routine, it will be wrapped to generic code at run-time.
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*/
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#define __inb(p) sh_mv.mv_inb((p))
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#define __inw(p) sh_mv.mv_inw((p))
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#define __inl(p) sh_mv.mv_inl((p))
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#define __outb(x,p) sh_mv.mv_outb((x),(p))
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#define __outw(x,p) sh_mv.mv_outw((x),(p))
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#define __outl(x,p) sh_mv.mv_outl((x),(p))
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#define __inb_p(p) sh_mv.mv_inb_p((p))
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#define __inw_p(p) sh_mv.mv_inw_p((p))
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#define __inl_p(p) sh_mv.mv_inl_p((p))
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#define __outb_p(x,p) sh_mv.mv_outb_p((x),(p))
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#define __outw_p(x,p) sh_mv.mv_outw_p((x),(p))
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#define __outl_p(x,p) sh_mv.mv_outl_p((x),(p))
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#define __insb(p,b,c) sh_mv.mv_insb((p), (b), (c))
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#define __insw(p,b,c) sh_mv.mv_insw((p), (b), (c))
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#define __insl(p,b,c) sh_mv.mv_insl((p), (b), (c))
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#define __outsb(p,b,c) sh_mv.mv_outsb((p), (b), (c))
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#define __outsw(p,b,c) sh_mv.mv_outsw((p), (b), (c))
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#define __outsl(p,b,c) sh_mv.mv_outsl((p), (b), (c))
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#define __readb(a) sh_mv.mv_readb((a))
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#define __readw(a) sh_mv.mv_readw((a))
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#define __readl(a) sh_mv.mv_readl((a))
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#define __writeb(v,a) sh_mv.mv_writeb((v),(a))
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#define __writew(v,a) sh_mv.mv_writew((v),(a))
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#define __writel(v,a) sh_mv.mv_writel((v),(a))
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#define inb __inb
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#define inw __inw
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#define inl __inl
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#define outb __outb
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#define outw __outw
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#define outl __outl
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#define inb_p __inb_p
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#define inw_p __inw_p
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#define inl_p __inl_p
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#define outb_p __outb_p
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#define outw_p __outw_p
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#define outl_p __outl_p
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#define insb __insb
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#define insw __insw
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#define insl __insl
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#define outsb __outsb
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#define outsw __outsw
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#define outsl __outsl
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#define __raw_readb(a) __readb((void __iomem *)(a))
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#define __raw_readw(a) __readw((void __iomem *)(a))
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#define __raw_readl(a) __readl((void __iomem *)(a))
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#define __raw_writeb(v, a) __writeb(v, (void __iomem *)(a))
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#define __raw_writew(v, a) __writew(v, (void __iomem *)(a))
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#define __raw_writel(v, a) __writel(v, (void __iomem *)(a))
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void __raw_writesl(unsigned long addr, const void *data, int longlen);
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void __raw_readsl(unsigned long addr, void *data, int longlen);
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/*
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* The platform header files may define some of these macros to use
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* the inlined versions where appropriate. These macros may also be
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* redefined by userlevel programs.
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*/
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#ifdef __readb
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# define readb(a) ({ unsigned int r_ = __raw_readb(a); mb(); r_; })
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#endif
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#ifdef __raw_readw
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# define readw(a) ({ unsigned int r_ = __raw_readw(a); mb(); r_; })
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#endif
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#ifdef __raw_readl
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# define readl(a) ({ unsigned int r_ = __raw_readl(a); mb(); r_; })
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#endif
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#ifdef __raw_writeb
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# define writeb(v,a) ({ __raw_writeb((v),(a)); mb(); })
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#endif
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#ifdef __raw_writew
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# define writew(v,a) ({ __raw_writew((v),(a)); mb(); })
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#endif
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#ifdef __raw_writel
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# define writel(v,a) ({ __raw_writel((v),(a)); mb(); })
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#endif
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#define __BUILD_MEMORY_STRING(bwlq, type) \
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\
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static inline void writes##bwlq(volatile void __iomem *mem, \
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const void *addr, unsigned int count) \
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{ \
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const volatile type *__addr = addr; \
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\
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while (count--) { \
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__raw_write##bwlq(*__addr, mem); \
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__addr++; \
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} \
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} \
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\
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static inline void reads##bwlq(volatile void __iomem *mem, void *addr, \
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unsigned int count) \
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{ \
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volatile type *__addr = addr; \
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\
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while (count--) { \
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*__addr = __raw_read##bwlq(mem); \
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__addr++; \
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} \
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}
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__BUILD_MEMORY_STRING(b, u8)
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__BUILD_MEMORY_STRING(w, u16)
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#define writesl __raw_writesl
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#define readsl __raw_readsl
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#define readb_relaxed(a) readb(a)
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#define readw_relaxed(a) readw(a)
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#define readl_relaxed(a) readl(a)
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/* Simple MMIO */
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#define ioread8(a) readb(a)
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#define ioread16(a) readw(a)
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#define ioread16be(a) be16_to_cpu(__raw_readw((a)))
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#define ioread32(a) readl(a)
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#define ioread32be(a) be32_to_cpu(__raw_readl((a)))
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#define iowrite8(v,a) writeb((v),(a))
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#define iowrite16(v,a) writew((v),(a))
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#define iowrite16be(v,a) __raw_writew(cpu_to_be16((v)),(a))
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#define iowrite32(v,a) writel((v),(a))
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#define iowrite32be(v,a) __raw_writel(cpu_to_be32((v)),(a))
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#define ioread8_rep(a,d,c) insb((a),(d),(c))
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#define ioread16_rep(a,d,c) insw((a),(d),(c))
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#define ioread32_rep(a,d,c) insl((a),(d),(c))
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#define iowrite8_rep(a,s,c) outsb((a),(s),(c))
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#define iowrite16_rep(a,s,c) outsw((a),(s),(c))
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#define iowrite32_rep(a,s,c) outsl((a),(s),(c))
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#define mmiowb() wmb() /* synco on SH-4A, otherwise a nop */
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#define IO_SPACE_LIMIT 0xffffffff
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/*
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* This function provides a method for the generic case where a board-specific
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* ioport_map simply needs to return the port + some arbitrary port base.
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*
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* We use this at board setup time to implicitly set the port base, and
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* as a result, we can use the generic ioport_map.
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*/
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static inline void __set_io_port_base(unsigned long pbase)
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{
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extern unsigned long generic_io_base;
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generic_io_base = pbase;
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}
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#define __ioport_map(p, n) sh_mv.mv_ioport_map((p), (n))
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/* We really want to try and get these to memcpy etc */
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extern void memcpy_fromio(void *, volatile void __iomem *, unsigned long);
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extern void memcpy_toio(volatile void __iomem *, const void *, unsigned long);
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extern void memset_io(volatile void __iomem *, int, unsigned long);
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/* SuperH on-chip I/O functions */
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static inline unsigned char ctrl_inb(unsigned long addr)
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{
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return *(volatile unsigned char*)addr;
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}
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static inline unsigned short ctrl_inw(unsigned long addr)
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{
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return *(volatile unsigned short*)addr;
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}
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static inline unsigned int ctrl_inl(unsigned long addr)
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{
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return *(volatile unsigned long*)addr;
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}
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static inline unsigned long long ctrl_inq(unsigned long addr)
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{
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return *(volatile unsigned long long*)addr;
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}
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static inline void ctrl_outb(unsigned char b, unsigned long addr)
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{
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*(volatile unsigned char*)addr = b;
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}
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static inline void ctrl_outw(unsigned short b, unsigned long addr)
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{
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*(volatile unsigned short*)addr = b;
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}
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static inline void ctrl_outl(unsigned int b, unsigned long addr)
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{
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*(volatile unsigned long*)addr = b;
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}
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static inline void ctrl_outq(unsigned long long b, unsigned long addr)
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{
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*(volatile unsigned long long*)addr = b;
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}
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static inline void ctrl_delay(void)
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{
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#ifdef P2SEG
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ctrl_inw(P2SEG);
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#endif
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}
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/* Quad-word real-mode I/O, don't ask.. */
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unsigned long long peek_real_address_q(unsigned long long addr);
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unsigned long long poke_real_address_q(unsigned long long addr,
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unsigned long long val);
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/* arch/sh/mm/ioremap_64.c */
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unsigned long onchip_remap(unsigned long addr, unsigned long size,
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const char *name);
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extern void onchip_unmap(unsigned long vaddr);
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#if !defined(CONFIG_MMU)
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#define virt_to_phys(address) ((unsigned long)(address))
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#define phys_to_virt(address) ((void *)(address))
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#else
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#define virt_to_phys(address) (__pa(address))
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#define phys_to_virt(address) (__va(address))
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#endif
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/*
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* On 32-bit SH, we traditionally have the whole physical address space
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* mapped at all times (as MIPS does), so "ioremap()" and "iounmap()" do
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* not need to do anything but place the address in the proper segment.
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* This is true for P1 and P2 addresses, as well as some P3 ones.
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* However, most of the P3 addresses and newer cores using extended
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* addressing need to map through page tables, so the ioremap()
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* implementation becomes a bit more complicated.
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*
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* See arch/sh/mm/ioremap.c for additional notes on this.
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*
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* We cheat a bit and always return uncachable areas until we've fixed
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* the drivers to handle caching properly.
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*
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* On the SH-5 the concept of segmentation in the 1:1 PXSEG sense simply
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* doesn't exist, so everything must go through page tables.
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*/
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#ifdef CONFIG_MMU
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void __iomem *__ioremap(unsigned long offset, unsigned long size,
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unsigned long flags);
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void __iounmap(void __iomem *addr);
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#else
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#define __ioremap(offset, size, flags) ((void __iomem *)(offset))
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#define __iounmap(addr) do { } while (0)
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#endif /* CONFIG_MMU */
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static inline void __iomem *
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__ioremap_mode(unsigned long offset, unsigned long size, unsigned long flags)
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{
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#ifdef CONFIG_SUPERH32
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unsigned long last_addr = offset + size - 1;
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#endif
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void __iomem *ret;
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ret = __ioremap_trapped(offset, size);
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if (ret)
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return ret;
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#ifdef CONFIG_SUPERH32
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/*
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* For P1 and P2 space this is trivial, as everything is already
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* mapped. Uncached access for P1 addresses are done through P2.
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* In the P3 case or for addresses outside of the 29-bit space,
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* mapping must be done by the PMB or by using page tables.
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*/
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if (likely(PXSEG(offset) < P3SEG && PXSEG(last_addr) < P3SEG)) {
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if (unlikely(flags & _PAGE_CACHABLE))
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return (void __iomem *)P1SEGADDR(offset);
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return (void __iomem *)P2SEGADDR(offset);
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}
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#endif
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return __ioremap(offset, size, flags);
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}
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#define ioremap(offset, size) \
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__ioremap_mode((offset), (size), 0)
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#define ioremap_nocache(offset, size) \
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__ioremap_mode((offset), (size), 0)
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#define ioremap_cache(offset, size) \
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__ioremap_mode((offset), (size), _PAGE_CACHABLE)
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#define p3_ioremap(offset, size, flags) \
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__ioremap((offset), (size), (flags))
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#define iounmap(addr) \
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__iounmap((addr))
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/*
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* Convert a physical pointer to a virtual kernel pointer for /dev/mem
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* access
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*/
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#define xlate_dev_mem_ptr(p) __va(p)
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/*
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* Convert a virtual cached pointer to an uncached pointer
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*/
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#define xlate_dev_kmem_ptr(p) p
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#endif /* __KERNEL__ */
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#endif /* __ASM_SH_IO_H */
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