9d325f2341
The S3C64XX timer is running at the wrong rate due to the assumptions made in the timer initialisation about the way the pwm dividers work. This means that time on the S3C64XX runs twice as fast as it should. Fix the problem by moving to using the clk framework to setup the pwm timer clock muxes, as the pwm-clock code has all the necessary knowledge of how the timer clock inputs are routed. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
278 lines
6.6 KiB
C
278 lines
6.6 KiB
C
/* linux/arch/arm/mach-s3c2410/clock.c
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*
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* Copyright (c) 2006 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* S3C2410,S3C2440,S3C2442 Clock control support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/sysdev.h>
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#include <linux/clk.h>
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#include <linux/mutex.h>
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#include <linux/delay.h>
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#include <linux/serial_core.h>
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#include <linux/io.h>
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#include <asm/mach/map.h>
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#include <mach/hardware.h>
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#include <plat/regs-serial.h>
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#include <mach/regs-clock.h>
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#include <mach/regs-gpio.h>
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#include <plat/s3c2410.h>
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#include <plat/clock.h>
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#include <plat/cpu.h>
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int s3c2410_clkcon_enable(struct clk *clk, int enable)
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{
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unsigned int clocks = clk->ctrlbit;
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unsigned long clkcon;
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clkcon = __raw_readl(S3C2410_CLKCON);
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if (enable)
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clkcon |= clocks;
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else
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clkcon &= ~clocks;
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/* ensure none of the special function bits set */
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clkcon &= ~(S3C2410_CLKCON_IDLE|S3C2410_CLKCON_POWER);
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__raw_writel(clkcon, S3C2410_CLKCON);
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return 0;
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}
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static int s3c2410_upll_enable(struct clk *clk, int enable)
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{
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unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);
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unsigned long orig = clkslow;
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if (enable)
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clkslow &= ~S3C2410_CLKSLOW_UCLK_OFF;
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else
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clkslow |= S3C2410_CLKSLOW_UCLK_OFF;
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__raw_writel(clkslow, S3C2410_CLKSLOW);
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/* if we started the UPLL, then allow to settle */
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if (enable && (orig & S3C2410_CLKSLOW_UCLK_OFF))
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udelay(200);
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return 0;
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}
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/* standard clock definitions */
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static struct clk init_clocks_disable[] = {
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{
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.name = "nand",
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.id = -1,
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.parent = &clk_h,
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.enable = s3c2410_clkcon_enable,
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.ctrlbit = S3C2410_CLKCON_NAND,
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}, {
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.name = "sdi",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c2410_clkcon_enable,
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.ctrlbit = S3C2410_CLKCON_SDI,
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}, {
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.name = "adc",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c2410_clkcon_enable,
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.ctrlbit = S3C2410_CLKCON_ADC,
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}, {
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.name = "i2c",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c2410_clkcon_enable,
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.ctrlbit = S3C2410_CLKCON_IIC,
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}, {
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.name = "iis",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c2410_clkcon_enable,
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.ctrlbit = S3C2410_CLKCON_IIS,
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}, {
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.name = "spi",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c2410_clkcon_enable,
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.ctrlbit = S3C2410_CLKCON_SPI,
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}
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};
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static struct clk init_clocks[] = {
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{
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.name = "lcd",
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.id = -1,
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.parent = &clk_h,
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.enable = s3c2410_clkcon_enable,
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.ctrlbit = S3C2410_CLKCON_LCDC,
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}, {
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.name = "gpio",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c2410_clkcon_enable,
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.ctrlbit = S3C2410_CLKCON_GPIO,
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}, {
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.name = "usb-host",
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.id = -1,
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.parent = &clk_h,
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.enable = s3c2410_clkcon_enable,
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.ctrlbit = S3C2410_CLKCON_USBH,
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}, {
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.name = "usb-device",
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.id = -1,
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.parent = &clk_h,
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.enable = s3c2410_clkcon_enable,
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.ctrlbit = S3C2410_CLKCON_USBD,
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}, {
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.name = "timers",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c2410_clkcon_enable,
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.ctrlbit = S3C2410_CLKCON_PWMT,
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}, {
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.name = "uart",
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.id = 0,
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.parent = &clk_p,
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.enable = s3c2410_clkcon_enable,
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.ctrlbit = S3C2410_CLKCON_UART0,
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}, {
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.name = "uart",
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.id = 1,
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.parent = &clk_p,
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.enable = s3c2410_clkcon_enable,
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.ctrlbit = S3C2410_CLKCON_UART1,
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}, {
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.name = "uart",
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.id = 2,
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.parent = &clk_p,
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.enable = s3c2410_clkcon_enable,
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.ctrlbit = S3C2410_CLKCON_UART2,
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}, {
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.name = "rtc",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c2410_clkcon_enable,
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.ctrlbit = S3C2410_CLKCON_RTC,
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}, {
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.name = "watchdog",
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.id = -1,
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.parent = &clk_p,
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.ctrlbit = 0,
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}, {
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.name = "usb-bus-host",
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.id = -1,
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.parent = &clk_usb_bus,
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}, {
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.name = "usb-bus-gadget",
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.id = -1,
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.parent = &clk_usb_bus,
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},
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};
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/* s3c2410_baseclk_add()
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*
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* Add all the clocks used by the s3c2410 or compatible CPUs
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* such as the S3C2440 and S3C2442.
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*
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* We cannot use a system device as we are needed before any
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* of the init-calls that initialise the devices are actually
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* done.
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*/
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int __init s3c2410_baseclk_add(void)
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{
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unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);
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unsigned long clkcon = __raw_readl(S3C2410_CLKCON);
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struct clk *clkp;
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struct clk *xtal;
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int ret;
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int ptr;
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clk_upll.enable = s3c2410_upll_enable;
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if (s3c24xx_register_clock(&clk_usb_bus) < 0)
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printk(KERN_ERR "failed to register usb bus clock\n");
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/* register clocks from clock array */
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clkp = init_clocks;
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for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
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/* ensure that we note the clock state */
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clkp->usage = clkcon & clkp->ctrlbit ? 1 : 0;
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ret = s3c24xx_register_clock(clkp);
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if (ret < 0) {
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printk(KERN_ERR "Failed to register clock %s (%d)\n",
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clkp->name, ret);
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}
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}
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/* We must be careful disabling the clocks we are not intending to
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* be using at boot time, as subsystems such as the LCD which do
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* their own DMA requests to the bus can cause the system to lockup
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* if they where in the middle of requesting bus access.
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*
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* Disabling the LCD clock if the LCD is active is very dangerous,
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* and therefore the bootloader should be careful to not enable
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* the LCD clock if it is not needed.
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*/
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/* install (and disable) the clocks we do not need immediately */
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clkp = init_clocks_disable;
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for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
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ret = s3c24xx_register_clock(clkp);
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if (ret < 0) {
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printk(KERN_ERR "Failed to register clock %s (%d)\n",
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clkp->name, ret);
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}
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s3c2410_clkcon_enable(clkp, 0);
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}
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/* show the clock-slow value */
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xtal = clk_get(NULL, "xtal");
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printk("CLOCK: Slow mode (%ld.%ld MHz), %s, MPLL %s, UPLL %s\n",
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print_mhz(clk_get_rate(xtal) /
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( 2 * S3C2410_CLKSLOW_GET_SLOWVAL(clkslow))),
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(clkslow & S3C2410_CLKSLOW_SLOW) ? "slow" : "fast",
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(clkslow & S3C2410_CLKSLOW_MPLL_OFF) ? "off" : "on",
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(clkslow & S3C2410_CLKSLOW_UCLK_OFF) ? "off" : "on");
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s3c_pwmclk_init();
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return 0;
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}
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