e24c2d963a
After seeing, at best, "guesses" as to the following kind of information in several drivers, I decided that we really need a way for platforms to specifically give advice in this area for what works best with their PCI controller implementation. Basically, this new interface gives DMA bursting advice on PCI. There are three forms of the advice: 1) Burst as much as possible, it is not necessary to end bursts on some particular boundary for best performance. 2) Burst on some byte count multiple. A DMA burst to some multiple of number of bytes may be done, but it is important to end the burst on an exact multiple for best performance. The best example of this I am aware of are the PPC64 PCI controllers, where if you end a burst mid-cacheline then chip has to refetch the data and the IOMMU translations which hurts performance a lot. 3) Burst on a single byte count multiple. Bursts shall end exactly on the next multiple boundary for best performance. Sparc64 and Alpha's PCI controllers operate this way. They disconnect any device which tries to burst across a cacheline boundary. Actually, newer sparc64 PCI controllers do not have this behavior. That is why the "pdev" is passed into the interface, so I can add code later to check which PCI controller the system is using and give advice accordingly. Signed-off-by: David S. Miller <davem@davemloft.net> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
159 lines
4.8 KiB
C
159 lines
4.8 KiB
C
#ifndef _ASM_IA64_PCI_H
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#define _ASM_IA64_PCI_H
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#include <linux/mm.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/string.h>
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#include <linux/types.h>
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#include <asm/io.h>
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#include <asm/scatterlist.h>
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/*
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* Can be used to override the logic in pci_scan_bus for skipping already-configured bus
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* numbers - to be used for buggy BIOSes or architectures with incomplete PCI setup by the
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* loader.
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*/
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#define pcibios_assign_all_busses() 0
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#define pcibios_scan_all_fns(a, b) 0
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#define PCIBIOS_MIN_IO 0x1000
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#define PCIBIOS_MIN_MEM 0x10000000
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void pcibios_config_init(void);
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struct pci_dev;
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/*
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* PCI_DMA_BUS_IS_PHYS should be set to 1 if there is _necessarily_ a direct correspondence
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* between device bus addresses and CPU physical addresses. Platforms with a hardware I/O
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* MMU _must_ turn this off to suppress the bounce buffer handling code in the block and
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* network device layers. Platforms with separate bus address spaces _must_ turn this off
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* and provide a device DMA mapping implementation that takes care of the necessary
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* address translation.
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*
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* For now, the ia64 platforms which may have separate/multiple bus address spaces all
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* have I/O MMUs which support the merging of physically discontiguous buffers, so we can
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* use that as the sole factor to determine the setting of PCI_DMA_BUS_IS_PHYS.
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*/
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extern unsigned long ia64_max_iommu_merge_mask;
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#define PCI_DMA_BUS_IS_PHYS (ia64_max_iommu_merge_mask == ~0UL)
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static inline void
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pcibios_set_master (struct pci_dev *dev)
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{
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/* No special bus mastering setup handling */
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}
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static inline void
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pcibios_penalize_isa_irq (int irq)
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{
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/* We don't do dynamic PCI IRQ allocation */
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}
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#define HAVE_ARCH_PCI_MWI 1
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extern int pcibios_prep_mwi (struct pci_dev *);
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#include <asm-generic/pci-dma-compat.h>
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/* pci_unmap_{single,page} is not a nop, thus... */
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#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \
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dma_addr_t ADDR_NAME;
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#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \
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__u32 LEN_NAME;
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#define pci_unmap_addr(PTR, ADDR_NAME) \
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((PTR)->ADDR_NAME)
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#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \
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(((PTR)->ADDR_NAME) = (VAL))
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#define pci_unmap_len(PTR, LEN_NAME) \
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((PTR)->LEN_NAME)
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#define pci_unmap_len_set(PTR, LEN_NAME, VAL) \
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(((PTR)->LEN_NAME) = (VAL))
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/* The ia64 platform always supports 64-bit addressing. */
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#define pci_dac_dma_supported(pci_dev, mask) (1)
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#define pci_dac_page_to_dma(dev,pg,off,dir) ((dma_addr_t) page_to_bus(pg) + (off))
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#define pci_dac_dma_to_page(dev,dma_addr) (virt_to_page(bus_to_virt(dma_addr)))
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#define pci_dac_dma_to_offset(dev,dma_addr) offset_in_page(dma_addr)
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#define pci_dac_dma_sync_single_for_cpu(dev,dma_addr,len,dir) do { } while (0)
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#define pci_dac_dma_sync_single_for_device(dev,dma_addr,len,dir) do { mb(); } while (0)
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#define sg_dma_len(sg) ((sg)->dma_length)
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#define sg_dma_address(sg) ((sg)->dma_address)
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static inline void pci_dma_burst_advice(struct pci_dev *pdev,
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enum pci_dma_burst_strategy *strat,
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unsigned long *strategy_parameter)
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{
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unsigned long cacheline_size;
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u8 byte;
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pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
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if (byte == 0)
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cacheline_size = 1024;
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else
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cacheline_size = (int) byte * 4;
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*strat = PCI_DMA_BURST_MULTIPLE;
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*strategy_parameter = cacheline_size;
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}
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#define HAVE_PCI_MMAP
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extern int pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma,
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enum pci_mmap_state mmap_state, int write_combine);
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#define HAVE_PCI_LEGACY
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extern int pci_mmap_legacy_page_range(struct pci_bus *bus,
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struct vm_area_struct *vma);
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extern ssize_t pci_read_legacy_io(struct kobject *kobj, char *buf, loff_t off,
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size_t count);
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extern ssize_t pci_write_legacy_io(struct kobject *kobj, char *buf, loff_t off,
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size_t count);
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extern int pci_mmap_legacy_mem(struct kobject *kobj,
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struct bin_attribute *attr,
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struct vm_area_struct *vma);
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#define pci_get_legacy_mem platform_pci_get_legacy_mem
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#define pci_legacy_read platform_pci_legacy_read
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#define pci_legacy_write platform_pci_legacy_write
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struct pci_window {
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struct resource resource;
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u64 offset;
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};
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struct pci_controller {
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void *acpi_handle;
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void *iommu;
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int segment;
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unsigned int windows;
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struct pci_window *window;
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void *platform_data;
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};
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#define PCI_CONTROLLER(busdev) ((struct pci_controller *) busdev->sysdata)
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#define pci_domain_nr(busdev) (PCI_CONTROLLER(busdev)->segment)
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extern struct pci_ops pci_root_ops;
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static inline int pci_proc_domain(struct pci_bus *bus)
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{
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return (pci_domain_nr(bus) != 0);
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}
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static inline void pcibios_add_platform_entries(struct pci_dev *dev)
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{
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}
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extern void pcibios_resource_to_bus(struct pci_dev *dev,
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struct pci_bus_region *region, struct resource *res);
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extern void pcibios_bus_to_resource(struct pci_dev *dev,
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struct resource *res, struct pci_bus_region *region);
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#define pcibios_scan_all_fns(a, b) 0
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#endif /* _ASM_IA64_PCI_H */
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