e193325e3e
This patch implement GPIO LIB support for the CPM2 GPIOs. The code can also be used for CPM1 GPIO port E, as both cores are compatible at the register level. Based on earlier work by Laurent Pinchart. Signed-off-by: Jochen Friedrich <jochen@scram.de> Cc: Laurent Pinchart <laurentp@cse-semaphore.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
391 lines
8.8 KiB
C
391 lines
8.8 KiB
C
/*
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* General Purpose functions for the global management of the
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* 8260 Communication Processor Module.
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* Copyright (c) 1999-2001 Dan Malek <dan@embeddedalley.com>
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* Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com)
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* 2.3.99 Updates
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*
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* 2006 (c) MontaVista Software, Inc.
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* Vitaly Bordug <vbordug@ru.mvista.com>
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* Merged to arch/powerpc from arch/ppc/syslib/cpm2_common.c
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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/*
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*
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* In addition to the individual control of the communication
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* channels, there are a few functions that globally affect the
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* communication processor.
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*
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* Buffer descriptors must be allocated from the dual ported memory
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* space. The allocator for that is here. When the communication
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* process is reset, we reclaim the memory available. There is
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* currently no deallocator for this memory.
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*/
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#include <linux/errno.h>
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/param.h>
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#include <linux/string.h>
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#include <linux/mm.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/mpc8260.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/cpm2.h>
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#include <asm/rheap.h>
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#include <asm/fs_pd.h>
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#include <sysdev/fsl_soc.h>
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cpm_cpm2_t __iomem *cpmp; /* Pointer to comm processor space */
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/* We allocate this here because it is used almost exclusively for
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* the communication processor devices.
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*/
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cpm2_map_t __iomem *cpm2_immr;
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#define CPM_MAP_SIZE (0x40000) /* 256k - the PQ3 reserve this amount
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of space for CPM as it is larger
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than on PQ2 */
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void __init cpm2_reset(void)
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{
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#ifdef CONFIG_PPC_85xx
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cpm2_immr = ioremap(CPM_MAP_ADDR, CPM_MAP_SIZE);
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#else
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cpm2_immr = ioremap(get_immrbase(), CPM_MAP_SIZE);
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#endif
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/* Reclaim the DP memory for our use.
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*/
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cpm_muram_init();
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/* Tell everyone where the comm processor resides.
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*/
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cpmp = &cpm2_immr->im_cpm;
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#ifndef CONFIG_PPC_EARLY_DEBUG_CPM
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/* Reset the CPM.
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*/
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cpm_command(CPM_CR_RST, 0);
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#endif
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}
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static DEFINE_SPINLOCK(cmd_lock);
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#define MAX_CR_CMD_LOOPS 10000
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int cpm_command(u32 command, u8 opcode)
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{
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int i, ret;
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unsigned long flags;
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spin_lock_irqsave(&cmd_lock, flags);
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ret = 0;
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out_be32(&cpmp->cp_cpcr, command | opcode | CPM_CR_FLG);
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for (i = 0; i < MAX_CR_CMD_LOOPS; i++)
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if ((in_be32(&cpmp->cp_cpcr) & CPM_CR_FLG) == 0)
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goto out;
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printk(KERN_ERR "%s(): Not able to issue CPM command\n", __func__);
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ret = -EIO;
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out:
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spin_unlock_irqrestore(&cmd_lock, flags);
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return ret;
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}
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EXPORT_SYMBOL(cpm_command);
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/* Set a baud rate generator. This needs lots of work. There are
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* eight BRGs, which can be connected to the CPM channels or output
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* as clocks. The BRGs are in two different block of internal
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* memory mapped space.
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* The baud rate clock is the system clock divided by something.
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* It was set up long ago during the initial boot phase and is
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* is given to us.
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* Baud rate clocks are zero-based in the driver code (as that maps
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* to port numbers). Documentation uses 1-based numbering.
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*/
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#define BRG_INT_CLK (get_brgfreq())
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#define BRG_UART_CLK (BRG_INT_CLK/16)
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/* This function is used by UARTS, or anything else that uses a 16x
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* oversampled clock.
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*/
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void
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cpm_setbrg(uint brg, uint rate)
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{
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u32 __iomem *bp;
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/* This is good enough to get SMCs running.....
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*/
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if (brg < 4) {
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bp = cpm2_map_size(im_brgc1, 16);
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} else {
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bp = cpm2_map_size(im_brgc5, 16);
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brg -= 4;
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}
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bp += brg;
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out_be32(bp, (((BRG_UART_CLK / rate) - 1) << 1) | CPM_BRG_EN);
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cpm2_unmap(bp);
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}
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/* This function is used to set high speed synchronous baud rate
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* clocks.
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*/
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void
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cpm2_fastbrg(uint brg, uint rate, int div16)
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{
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u32 __iomem *bp;
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u32 val;
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if (brg < 4) {
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bp = cpm2_map_size(im_brgc1, 16);
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} else {
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bp = cpm2_map_size(im_brgc5, 16);
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brg -= 4;
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}
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bp += brg;
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val = ((BRG_INT_CLK / rate) << 1) | CPM_BRG_EN;
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if (div16)
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val |= CPM_BRG_DIV16;
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out_be32(bp, val);
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cpm2_unmap(bp);
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}
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int cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode)
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{
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int ret = 0;
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int shift;
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int i, bits = 0;
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cpmux_t __iomem *im_cpmux;
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u32 __iomem *reg;
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u32 mask = 7;
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u8 clk_map[][3] = {
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{CPM_CLK_FCC1, CPM_BRG5, 0},
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{CPM_CLK_FCC1, CPM_BRG6, 1},
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{CPM_CLK_FCC1, CPM_BRG7, 2},
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{CPM_CLK_FCC1, CPM_BRG8, 3},
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{CPM_CLK_FCC1, CPM_CLK9, 4},
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{CPM_CLK_FCC1, CPM_CLK10, 5},
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{CPM_CLK_FCC1, CPM_CLK11, 6},
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{CPM_CLK_FCC1, CPM_CLK12, 7},
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{CPM_CLK_FCC2, CPM_BRG5, 0},
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{CPM_CLK_FCC2, CPM_BRG6, 1},
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{CPM_CLK_FCC2, CPM_BRG7, 2},
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{CPM_CLK_FCC2, CPM_BRG8, 3},
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{CPM_CLK_FCC2, CPM_CLK13, 4},
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{CPM_CLK_FCC2, CPM_CLK14, 5},
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{CPM_CLK_FCC2, CPM_CLK15, 6},
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{CPM_CLK_FCC2, CPM_CLK16, 7},
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{CPM_CLK_FCC3, CPM_BRG5, 0},
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{CPM_CLK_FCC3, CPM_BRG6, 1},
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{CPM_CLK_FCC3, CPM_BRG7, 2},
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{CPM_CLK_FCC3, CPM_BRG8, 3},
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{CPM_CLK_FCC3, CPM_CLK13, 4},
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{CPM_CLK_FCC3, CPM_CLK14, 5},
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{CPM_CLK_FCC3, CPM_CLK15, 6},
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{CPM_CLK_FCC3, CPM_CLK16, 7},
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{CPM_CLK_SCC1, CPM_BRG1, 0},
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{CPM_CLK_SCC1, CPM_BRG2, 1},
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{CPM_CLK_SCC1, CPM_BRG3, 2},
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{CPM_CLK_SCC1, CPM_BRG4, 3},
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{CPM_CLK_SCC1, CPM_CLK11, 4},
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{CPM_CLK_SCC1, CPM_CLK12, 5},
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{CPM_CLK_SCC1, CPM_CLK3, 6},
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{CPM_CLK_SCC1, CPM_CLK4, 7},
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{CPM_CLK_SCC2, CPM_BRG1, 0},
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{CPM_CLK_SCC2, CPM_BRG2, 1},
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{CPM_CLK_SCC2, CPM_BRG3, 2},
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{CPM_CLK_SCC2, CPM_BRG4, 3},
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{CPM_CLK_SCC2, CPM_CLK11, 4},
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{CPM_CLK_SCC2, CPM_CLK12, 5},
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{CPM_CLK_SCC2, CPM_CLK3, 6},
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{CPM_CLK_SCC2, CPM_CLK4, 7},
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{CPM_CLK_SCC3, CPM_BRG1, 0},
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{CPM_CLK_SCC3, CPM_BRG2, 1},
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{CPM_CLK_SCC3, CPM_BRG3, 2},
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{CPM_CLK_SCC3, CPM_BRG4, 3},
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{CPM_CLK_SCC3, CPM_CLK5, 4},
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{CPM_CLK_SCC3, CPM_CLK6, 5},
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{CPM_CLK_SCC3, CPM_CLK7, 6},
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{CPM_CLK_SCC3, CPM_CLK8, 7},
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{CPM_CLK_SCC4, CPM_BRG1, 0},
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{CPM_CLK_SCC4, CPM_BRG2, 1},
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{CPM_CLK_SCC4, CPM_BRG3, 2},
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{CPM_CLK_SCC4, CPM_BRG4, 3},
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{CPM_CLK_SCC4, CPM_CLK5, 4},
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{CPM_CLK_SCC4, CPM_CLK6, 5},
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{CPM_CLK_SCC4, CPM_CLK7, 6},
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{CPM_CLK_SCC4, CPM_CLK8, 7},
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};
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im_cpmux = cpm2_map(im_cpmux);
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switch (target) {
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case CPM_CLK_SCC1:
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reg = &im_cpmux->cmx_scr;
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shift = 24;
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break;
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case CPM_CLK_SCC2:
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reg = &im_cpmux->cmx_scr;
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shift = 16;
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break;
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case CPM_CLK_SCC3:
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reg = &im_cpmux->cmx_scr;
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shift = 8;
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break;
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case CPM_CLK_SCC4:
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reg = &im_cpmux->cmx_scr;
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shift = 0;
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break;
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case CPM_CLK_FCC1:
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reg = &im_cpmux->cmx_fcr;
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shift = 24;
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break;
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case CPM_CLK_FCC2:
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reg = &im_cpmux->cmx_fcr;
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shift = 16;
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break;
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case CPM_CLK_FCC3:
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reg = &im_cpmux->cmx_fcr;
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shift = 8;
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break;
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default:
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printk(KERN_ERR "cpm2_clock_setup: invalid clock target\n");
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return -EINVAL;
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}
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if (mode == CPM_CLK_RX)
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shift += 3;
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for (i = 0; i < ARRAY_SIZE(clk_map); i++) {
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if (clk_map[i][0] == target && clk_map[i][1] == clock) {
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bits = clk_map[i][2];
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break;
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}
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}
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if (i == ARRAY_SIZE(clk_map))
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ret = -EINVAL;
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bits <<= shift;
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mask <<= shift;
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out_be32(reg, (in_be32(reg) & ~mask) | bits);
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cpm2_unmap(im_cpmux);
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return ret;
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}
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int cpm2_smc_clk_setup(enum cpm_clk_target target, int clock)
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{
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int ret = 0;
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int shift;
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int i, bits = 0;
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cpmux_t __iomem *im_cpmux;
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u8 __iomem *reg;
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u8 mask = 3;
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u8 clk_map[][3] = {
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{CPM_CLK_SMC1, CPM_BRG1, 0},
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{CPM_CLK_SMC1, CPM_BRG7, 1},
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{CPM_CLK_SMC1, CPM_CLK7, 2},
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{CPM_CLK_SMC1, CPM_CLK9, 3},
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{CPM_CLK_SMC2, CPM_BRG2, 0},
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{CPM_CLK_SMC2, CPM_BRG8, 1},
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{CPM_CLK_SMC2, CPM_CLK4, 2},
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{CPM_CLK_SMC2, CPM_CLK15, 3},
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};
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im_cpmux = cpm2_map(im_cpmux);
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switch (target) {
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case CPM_CLK_SMC1:
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reg = &im_cpmux->cmx_smr;
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mask = 3;
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shift = 4;
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break;
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case CPM_CLK_SMC2:
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reg = &im_cpmux->cmx_smr;
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mask = 3;
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shift = 0;
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break;
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default:
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printk(KERN_ERR "cpm2_smc_clock_setup: invalid clock target\n");
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return -EINVAL;
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}
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for (i = 0; i < ARRAY_SIZE(clk_map); i++) {
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if (clk_map[i][0] == target && clk_map[i][1] == clock) {
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bits = clk_map[i][2];
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break;
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}
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}
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if (i == ARRAY_SIZE(clk_map))
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ret = -EINVAL;
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bits <<= shift;
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mask <<= shift;
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out_8(reg, (in_8(reg) & ~mask) | bits);
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cpm2_unmap(im_cpmux);
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return ret;
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}
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struct cpm2_ioports {
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u32 dir, par, sor, odr, dat;
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u32 res[3];
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};
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void cpm2_set_pin(int port, int pin, int flags)
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{
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struct cpm2_ioports __iomem *iop =
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(struct cpm2_ioports __iomem *)&cpm2_immr->im_ioport;
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pin = 1 << (31 - pin);
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if (flags & CPM_PIN_OUTPUT)
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setbits32(&iop[port].dir, pin);
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else
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clrbits32(&iop[port].dir, pin);
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if (!(flags & CPM_PIN_GPIO))
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setbits32(&iop[port].par, pin);
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else
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clrbits32(&iop[port].par, pin);
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if (flags & CPM_PIN_SECONDARY)
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setbits32(&iop[port].sor, pin);
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else
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clrbits32(&iop[port].sor, pin);
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if (flags & CPM_PIN_OPENDRAIN)
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setbits32(&iop[port].odr, pin);
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else
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clrbits32(&iop[port].odr, pin);
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}
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static int cpm_init_par_io(void)
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{
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struct device_node *np;
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for_each_compatible_node(np, NULL, "fsl,cpm2-pario-bank")
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cpm2_gpiochip_add32(np);
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return 0;
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}
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arch_initcall(cpm_init_par_io);
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