dcbc853af6
Prepare the code for the conversion of the ioat2 linked-list-ring into a native ring buffer. After this conversion ioat2 channels will share less of the ioat1 infrastructure, but there will still be places where sharing is possible. struct ioat_chan_common is created to house the channel attributes that will remain common between ioat1 and ioat2 channels. For every routine that accesses both common and hardware specific fields the old unified 'ioat_chan' pointer is split into an 'ioat' and 'chan' pointer. Where 'chan' references common fields and 'ioat' the hardware/version specific. [ Impact: pure structure member movement/variable renames, no logic changes ] Signed-off-by: Maciej Sosnowski <maciej.sosnowski@intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
173 lines
5.0 KiB
C
173 lines
5.0 KiB
C
/*
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* Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59
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* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called COPYING.
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*/
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#ifndef IOATDMA_H
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#define IOATDMA_H
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#include <linux/dmaengine.h>
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#include "hw.h"
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#include <linux/init.h>
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#include <linux/dmapool.h>
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#include <linux/cache.h>
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#include <linux/pci_ids.h>
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#include <net/tcp.h>
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#define IOAT_DMA_VERSION "3.64"
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#define IOAT_LOW_COMPLETION_MASK 0xffffffc0
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#define IOAT_DMA_DCA_ANY_CPU ~0
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#define IOAT_WATCHDOG_PERIOD (2 * HZ)
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#define to_ioatdma_device(dev) container_of(dev, struct ioatdma_device, common)
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#define to_ioat_desc(lh) container_of(lh, struct ioat_desc_sw, node)
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#define tx_to_ioat_desc(tx) container_of(tx, struct ioat_desc_sw, txd)
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#define to_dev(ioat_chan) (&(ioat_chan)->device->pdev->dev)
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#define chan_num(ch) ((int)((ch)->reg_base - (ch)->device->reg_base) / 0x80)
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#define RESET_DELAY msecs_to_jiffies(100)
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#define WATCHDOG_DELAY round_jiffies(msecs_to_jiffies(2000))
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/*
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* workaround for IOAT ver.3.0 null descriptor issue
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* (channel returns error when size is 0)
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*/
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#define NULL_DESC_BUFFER_SIZE 1
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/**
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* struct ioatdma_device - internal representation of a IOAT device
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* @pdev: PCI-Express device
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* @reg_base: MMIO register space base address
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* @dma_pool: for allocating DMA descriptors
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* @common: embedded struct dma_device
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* @version: version of ioatdma device
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* @msix_entries: irq handlers
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* @idx: per channel data
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* @dca: direct cache access context
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* @intr_quirk: interrupt setup quirk (for ioat_v1 devices)
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*/
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struct ioatdma_device {
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struct pci_dev *pdev;
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void __iomem *reg_base;
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struct pci_pool *dma_pool;
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struct pci_pool *completion_pool;
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struct dma_device common;
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u8 version;
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struct delayed_work work;
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struct msix_entry msix_entries[4];
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struct ioat_chan_common *idx[4];
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struct dca_provider *dca;
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void (*intr_quirk)(struct ioatdma_device *device);
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};
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struct ioat_chan_common {
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void __iomem *reg_base;
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unsigned long last_completion;
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unsigned long last_completion_time;
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spinlock_t cleanup_lock;
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dma_cookie_t completed_cookie;
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unsigned long watchdog_completion;
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int watchdog_tcp_cookie;
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u32 watchdog_last_tcp_cookie;
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struct delayed_work work;
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struct ioatdma_device *device;
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struct dma_chan common;
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dma_addr_t completion_addr;
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union {
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u64 full; /* HW completion writeback */
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struct {
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u32 low;
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u32 high;
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};
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} *completion_virt;
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unsigned long last_compl_desc_addr_hw;
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struct tasklet_struct cleanup_task;
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};
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/**
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* struct ioat_dma_chan - internal representation of a DMA channel
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*/
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struct ioat_dma_chan {
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struct ioat_chan_common base;
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size_t xfercap; /* XFERCAP register value expanded out */
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spinlock_t desc_lock;
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struct list_head free_desc;
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struct list_head used_desc;
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int pending;
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u16 dmacount;
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u16 desccount;
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};
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static inline struct ioat_chan_common *to_chan_common(struct dma_chan *c)
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{
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return container_of(c, struct ioat_chan_common, common);
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}
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static inline struct ioat_dma_chan *to_ioat_chan(struct dma_chan *c)
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{
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struct ioat_chan_common *chan = to_chan_common(c);
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return container_of(chan, struct ioat_dma_chan, base);
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}
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/* wrapper around hardware descriptor format + additional software fields */
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/**
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* struct ioat_desc_sw - wrapper around hardware descriptor
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* @hw: hardware DMA descriptor
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* @node: this descriptor will either be on the free list,
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* or attached to a transaction list (async_tx.tx_list)
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* @tx_cnt: number of descriptors required to complete the transaction
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* @txd: the generic software descriptor for all engines
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*/
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struct ioat_desc_sw {
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struct ioat_dma_descriptor *hw;
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struct list_head node;
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int tx_cnt;
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size_t len;
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dma_addr_t src;
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dma_addr_t dst;
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struct dma_async_tx_descriptor txd;
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};
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static inline void ioat_set_tcp_copy_break(unsigned long copybreak)
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{
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#ifdef CONFIG_NET_DMA
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sysctl_tcp_dma_copybreak = copybreak;
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#endif
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}
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int ioat1_dma_probe(struct ioatdma_device *dev, int dca);
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int ioat2_dma_probe(struct ioatdma_device *dev, int dca);
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int ioat3_dma_probe(struct ioatdma_device *dev, int dca);
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void ioat_dma_remove(struct ioatdma_device *device);
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struct dca_provider *ioat_dca_init(struct pci_dev *pdev, void __iomem *iobase);
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struct dca_provider *ioat2_dca_init(struct pci_dev *pdev, void __iomem *iobase);
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struct dca_provider *ioat3_dca_init(struct pci_dev *pdev, void __iomem *iobase);
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#endif /* IOATDMA_H */
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