dbf8471f52
Make the ppc32 pcibios_alloc_controller take a device node to match the ppc64 prototypes and have it set arch_data. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
239 lines
7.1 KiB
C
239 lines
7.1 KiB
C
/*
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* MPC86XX pci setup code
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*
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* Recode: ZHANG WEI <wei.zhang@freescale.com>
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* Initial author: Xianghua Xiao <x.xiao@freescale.com>
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*
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* Copyright 2006 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/types.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/serial.h>
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#include <asm/system.h>
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#include <asm/atomic.h>
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#include <asm/io.h>
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#include <asm/prom.h>
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#include <asm/pci-bridge.h>
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#include <sysdev/fsl_soc.h>
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#include <sysdev/fsl_pcie.h>
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#include "mpc86xx.h"
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#undef DEBUG
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#ifdef DEBUG
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#define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __FUNCTION__, ## args)
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#else
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#define DBG(fmt, args...)
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#endif
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struct pcie_outbound_window_regs {
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uint pexotar; /* 0x.0 - PCI Express outbound translation address register */
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uint pexotear; /* 0x.4 - PCI Express outbound translation extended address register */
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uint pexowbar; /* 0x.8 - PCI Express outbound window base address register */
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char res1[4];
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uint pexowar; /* 0x.10 - PCI Express outbound window attributes register */
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char res2[12];
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};
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struct pcie_inbound_window_regs {
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uint pexitar; /* 0x.0 - PCI Express inbound translation address register */
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char res1[4];
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uint pexiwbar; /* 0x.8 - PCI Express inbound window base address register */
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uint pexiwbear; /* 0x.c - PCI Express inbound window base extended address register */
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uint pexiwar; /* 0x.10 - PCI Express inbound window attributes register */
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char res2[12];
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};
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static void __init setup_pcie_atmu(struct pci_controller *hose, struct resource *rsrc)
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{
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volatile struct ccsr_pex *pcie;
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volatile struct pcie_outbound_window_regs *pcieow;
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volatile struct pcie_inbound_window_regs *pcieiw;
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int i = 0;
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DBG("PCIE memory map start 0x%x, size 0x%x\n", rsrc->start,
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rsrc->end - rsrc->start + 1);
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pcie = ioremap(rsrc->start, rsrc->end - rsrc->start + 1);
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/* Disable all windows (except pexowar0 since its ignored) */
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pcie->pexowar1 = 0;
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pcie->pexowar2 = 0;
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pcie->pexowar3 = 0;
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pcie->pexowar4 = 0;
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pcie->pexiwar1 = 0;
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pcie->pexiwar2 = 0;
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pcie->pexiwar3 = 0;
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pcieow = (struct pcie_outbound_window_regs *)&pcie->pexotar1;
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pcieiw = (struct pcie_inbound_window_regs *)&pcie->pexitar1;
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/* Setup outbound MEM window */
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for(i = 0; i < 3; i++)
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if (hose->mem_resources[i].flags & IORESOURCE_MEM){
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DBG("PCIE MEM resource start 0x%08x, size 0x%08x.\n",
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hose->mem_resources[i].start,
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hose->mem_resources[i].end
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- hose->mem_resources[i].start + 1);
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pcieow->pexotar = (hose->mem_resources[i].start) >> 12
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& 0x000fffff;
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pcieow->pexotear = 0;
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pcieow->pexowbar = (hose->mem_resources[i].start) >> 12
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& 0x000fffff;
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/* Enable, Mem R/W */
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pcieow->pexowar = 0x80044000 |
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(__ilog2(hose->mem_resources[i].end
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- hose->mem_resources[i].start + 1)
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- 1);
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pcieow++;
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}
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/* Setup outbound IO window */
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if (hose->io_resource.flags & IORESOURCE_IO){
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DBG("PCIE IO resource start 0x%08x, size 0x%08x, phy base 0x%08x.\n",
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hose->io_resource.start,
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hose->io_resource.end - hose->io_resource.start + 1,
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hose->io_base_phys);
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pcieow->pexotar = (hose->io_resource.start) >> 12 & 0x000fffff;
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pcieow->pexotear = 0;
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pcieow->pexowbar = (hose->io_base_phys) >> 12 & 0x000fffff;
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/* Enable, IO R/W */
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pcieow->pexowar = 0x80088000 | (__ilog2(hose->io_resource.end
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- hose->io_resource.start + 1) - 1);
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}
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/* Setup 2G inbound Memory Window @ 0 */
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pcieiw->pexitar = 0x00000000;
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pcieiw->pexiwbar = 0x00000000;
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/* Enable, Prefetch, Local Mem, Snoop R/W, 2G */
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pcieiw->pexiwar = 0xa0f5501e;
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}
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static void __init
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mpc86xx_setup_pcie(struct pci_controller *hose, u32 pcie_offset, u32 pcie_size)
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{
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u16 cmd;
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DBG("PCIE host controller register offset 0x%08x, size 0x%08x.\n",
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pcie_offset, pcie_size);
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early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
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cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
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| PCI_COMMAND_IO;
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early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
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early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
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}
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static void __devinit quirk_fsl_pcie_transparent(struct pci_dev *dev)
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{
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struct resource *res;
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int i, res_idx = PCI_BRIDGE_RESOURCES;
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struct pci_controller *hose;
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/*
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* Make the bridge be transparent.
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*/
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dev->transparent = 1;
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hose = pci_bus_to_hose(dev->bus->number);
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if (!hose) {
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printk(KERN_ERR "Can't find hose for bus %d\n",
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dev->bus->number);
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return;
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}
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if (hose->io_resource.flags) {
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res = &dev->resource[res_idx++];
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res->start = hose->io_resource.start;
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res->end = hose->io_resource.end;
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res->flags = hose->io_resource.flags;
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}
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for (i = 0; i < 3; i++) {
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res = &dev->resource[res_idx + i];
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res->start = hose->mem_resources[i].start;
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res->end = hose->mem_resources[i].end;
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res->flags = hose->mem_resources[i].flags;
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}
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}
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DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7010, quirk_fsl_pcie_transparent);
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DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7011, quirk_fsl_pcie_transparent);
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#define PCIE_LTSSM 0x404 /* PCIe Link Training and Status */
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#define PCIE_LTSSM_L0 0x16 /* L0 state */
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int __init mpc86xx_add_bridge(struct device_node *dev)
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{
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int len;
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struct pci_controller *hose;
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struct resource rsrc;
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const int *bus_range;
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int has_address = 0;
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int primary = 0;
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u16 val;
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DBG("Adding PCIE host bridge %s\n", dev->full_name);
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/* Fetch host bridge registers address */
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has_address = (of_address_to_resource(dev, 0, &rsrc) == 0);
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/* Get bus range if any */
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bus_range = of_get_property(dev, "bus-range", &len);
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if (bus_range == NULL || len < 2 * sizeof(int))
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printk(KERN_WARNING "Can't get bus-range for %s, assume"
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" bus 0\n", dev->full_name);
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pci_assign_all_buses = 1;
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hose = pcibios_alloc_controller(dev);
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if (!hose)
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return -ENOMEM;
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hose->indirect_type = PPC_INDIRECT_TYPE_EXT_REG |
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PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
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hose->first_busno = bus_range ? bus_range[0] : 0x0;
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hose->last_busno = bus_range ? bus_range[1] : 0xff;
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setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4);
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/* Probe the hose link training status */
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early_read_config_word(hose, 0, 0, PCIE_LTSSM, &val);
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if (val < PCIE_LTSSM_L0)
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return -ENXIO;
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/* Setup the PCIE host controller. */
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mpc86xx_setup_pcie(hose, rsrc.start, rsrc.end - rsrc.start + 1);
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if ((rsrc.start & 0xfffff) == 0x8000)
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primary = 1;
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printk(KERN_INFO "Found MPC86xx PCIE host bridge at 0x%08lx. "
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"Firmware bus number: %d->%d\n",
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(unsigned long) rsrc.start,
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hose->first_busno, hose->last_busno);
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DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
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hose, hose->cfg_addr, hose->cfg_data);
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/* Interpret the "ranges" property */
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/* This also maps the I/O region and sets isa_io/mem_base */
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pci_process_bridge_OF_ranges(hose, dev, primary);
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/* Setup PEX window registers */
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setup_pcie_atmu(hose, &rsrc);
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return 0;
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}
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