51533b615e
New CRIS sub architecture named v32. From: Dave Jones <davej@redhat.com> Fix swapped kmalloc args Signed-off-by: Mikael Starvik <starvik@axis.com> Signed-off-by: Dave Jones <davej@redhat.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
285 lines
9.4 KiB
C
285 lines
9.4 KiB
C
#ifndef __bif_core_defs_h
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#define __bif_core_defs_h
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/*
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* This file is autogenerated from
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* file: ../../inst/bif/rtl/bif_core_regs.r
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* id: bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp
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* last modfied: Mon Apr 11 16:06:33 2005
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*
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* by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_core_defs.h ../../inst/bif/rtl/bif_core_regs.r
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* id: $Id: bif_core_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $
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* Any changes here will be lost.
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*
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* -*- buffer-read-only: t -*-
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*/
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/* Main access macros */
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#ifndef REG_RD
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#define REG_RD( scope, inst, reg ) \
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REG_READ( reg_##scope##_##reg, \
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(inst) + REG_RD_ADDR_##scope##_##reg )
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#endif
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#ifndef REG_WR
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#define REG_WR( scope, inst, reg, val ) \
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REG_WRITE( reg_##scope##_##reg, \
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(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
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#endif
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#ifndef REG_RD_VECT
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#define REG_RD_VECT( scope, inst, reg, index ) \
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REG_READ( reg_##scope##_##reg, \
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(inst) + REG_RD_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg )
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#endif
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#ifndef REG_WR_VECT
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#define REG_WR_VECT( scope, inst, reg, index, val ) \
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REG_WRITE( reg_##scope##_##reg, \
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(inst) + REG_WR_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg, (val) )
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#endif
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#ifndef REG_RD_INT
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#define REG_RD_INT( scope, inst, reg ) \
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REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
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#endif
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#ifndef REG_WR_INT
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#define REG_WR_INT( scope, inst, reg, val ) \
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REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
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#endif
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#ifndef REG_RD_INT_VECT
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#define REG_RD_INT_VECT( scope, inst, reg, index ) \
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REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg )
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#endif
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#ifndef REG_WR_INT_VECT
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#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
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REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg, (val) )
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#endif
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#ifndef REG_TYPE_CONV
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#define REG_TYPE_CONV( type, orgtype, val ) \
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( { union { orgtype o; type n; } r; r.o = val; r.n; } )
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#endif
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#ifndef reg_page_size
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#define reg_page_size 8192
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#endif
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#ifndef REG_ADDR
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#define REG_ADDR( scope, inst, reg ) \
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( (inst) + REG_RD_ADDR_##scope##_##reg )
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#endif
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#ifndef REG_ADDR_VECT
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#define REG_ADDR_VECT( scope, inst, reg, index ) \
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( (inst) + REG_RD_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg )
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#endif
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/* C-code for register scope bif_core */
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/* Register rw_grp1_cfg, scope bif_core, type rw */
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typedef struct {
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unsigned int lw : 6;
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unsigned int ew : 3;
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unsigned int zw : 3;
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unsigned int aw : 2;
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unsigned int dw : 2;
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unsigned int ewb : 2;
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unsigned int bw : 1;
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unsigned int wr_extend : 1;
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unsigned int erc_en : 1;
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unsigned int mode : 1;
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unsigned int dummy1 : 10;
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} reg_bif_core_rw_grp1_cfg;
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#define REG_RD_ADDR_bif_core_rw_grp1_cfg 0
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#define REG_WR_ADDR_bif_core_rw_grp1_cfg 0
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/* Register rw_grp2_cfg, scope bif_core, type rw */
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typedef struct {
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unsigned int lw : 6;
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unsigned int ew : 3;
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unsigned int zw : 3;
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unsigned int aw : 2;
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unsigned int dw : 2;
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unsigned int ewb : 2;
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unsigned int bw : 1;
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unsigned int wr_extend : 1;
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unsigned int erc_en : 1;
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unsigned int mode : 1;
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unsigned int dummy1 : 10;
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} reg_bif_core_rw_grp2_cfg;
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#define REG_RD_ADDR_bif_core_rw_grp2_cfg 4
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#define REG_WR_ADDR_bif_core_rw_grp2_cfg 4
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/* Register rw_grp3_cfg, scope bif_core, type rw */
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typedef struct {
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unsigned int lw : 6;
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unsigned int ew : 3;
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unsigned int zw : 3;
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unsigned int aw : 2;
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unsigned int dw : 2;
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unsigned int ewb : 2;
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unsigned int bw : 1;
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unsigned int wr_extend : 1;
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unsigned int erc_en : 1;
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unsigned int mode : 1;
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unsigned int dummy1 : 2;
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unsigned int gated_csp0 : 2;
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unsigned int gated_csp1 : 2;
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unsigned int gated_csp2 : 2;
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unsigned int gated_csp3 : 2;
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} reg_bif_core_rw_grp3_cfg;
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#define REG_RD_ADDR_bif_core_rw_grp3_cfg 8
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#define REG_WR_ADDR_bif_core_rw_grp3_cfg 8
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/* Register rw_grp4_cfg, scope bif_core, type rw */
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typedef struct {
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unsigned int lw : 6;
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unsigned int ew : 3;
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unsigned int zw : 3;
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unsigned int aw : 2;
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unsigned int dw : 2;
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unsigned int ewb : 2;
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unsigned int bw : 1;
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unsigned int wr_extend : 1;
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unsigned int erc_en : 1;
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unsigned int mode : 1;
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unsigned int dummy1 : 4;
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unsigned int gated_csp4 : 2;
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unsigned int gated_csp5 : 2;
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unsigned int gated_csp6 : 2;
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} reg_bif_core_rw_grp4_cfg;
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#define REG_RD_ADDR_bif_core_rw_grp4_cfg 12
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#define REG_WR_ADDR_bif_core_rw_grp4_cfg 12
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/* Register rw_sdram_cfg_grp0, scope bif_core, type rw */
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typedef struct {
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unsigned int bank_sel : 5;
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unsigned int ca : 3;
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unsigned int type : 1;
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unsigned int bw : 1;
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unsigned int sh : 3;
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unsigned int wmm : 1;
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unsigned int sh16 : 1;
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unsigned int grp_sel : 5;
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unsigned int dummy1 : 12;
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} reg_bif_core_rw_sdram_cfg_grp0;
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#define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp0 16
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#define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp0 16
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/* Register rw_sdram_cfg_grp1, scope bif_core, type rw */
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typedef struct {
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unsigned int bank_sel : 5;
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unsigned int ca : 3;
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unsigned int type : 1;
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unsigned int bw : 1;
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unsigned int sh : 3;
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unsigned int wmm : 1;
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unsigned int sh16 : 1;
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unsigned int dummy1 : 17;
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} reg_bif_core_rw_sdram_cfg_grp1;
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#define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp1 20
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#define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp1 20
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/* Register rw_sdram_timing, scope bif_core, type rw */
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typedef struct {
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unsigned int cl : 3;
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unsigned int rcd : 3;
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unsigned int rp : 3;
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unsigned int rc : 2;
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unsigned int dpl : 2;
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unsigned int pde : 1;
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unsigned int ref : 2;
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unsigned int cpd : 1;
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unsigned int sdcke : 1;
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unsigned int sdclk : 1;
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unsigned int dummy1 : 13;
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} reg_bif_core_rw_sdram_timing;
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#define REG_RD_ADDR_bif_core_rw_sdram_timing 24
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#define REG_WR_ADDR_bif_core_rw_sdram_timing 24
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/* Register rw_sdram_cmd, scope bif_core, type rw */
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typedef struct {
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unsigned int cmd : 3;
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unsigned int mrs_data : 15;
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unsigned int dummy1 : 14;
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} reg_bif_core_rw_sdram_cmd;
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#define REG_RD_ADDR_bif_core_rw_sdram_cmd 28
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#define REG_WR_ADDR_bif_core_rw_sdram_cmd 28
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/* Register rs_sdram_ref_stat, scope bif_core, type rs */
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typedef struct {
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unsigned int ok : 1;
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unsigned int dummy1 : 31;
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} reg_bif_core_rs_sdram_ref_stat;
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#define REG_RD_ADDR_bif_core_rs_sdram_ref_stat 32
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/* Register r_sdram_ref_stat, scope bif_core, type r */
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typedef struct {
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unsigned int ok : 1;
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unsigned int dummy1 : 31;
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} reg_bif_core_r_sdram_ref_stat;
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#define REG_RD_ADDR_bif_core_r_sdram_ref_stat 36
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/* Constants */
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enum {
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regk_bif_core_bank2 = 0x00000000,
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regk_bif_core_bank4 = 0x00000001,
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regk_bif_core_bit10 = 0x0000000a,
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regk_bif_core_bit11 = 0x0000000b,
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regk_bif_core_bit12 = 0x0000000c,
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regk_bif_core_bit13 = 0x0000000d,
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regk_bif_core_bit14 = 0x0000000e,
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regk_bif_core_bit15 = 0x0000000f,
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regk_bif_core_bit16 = 0x00000010,
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regk_bif_core_bit17 = 0x00000011,
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regk_bif_core_bit18 = 0x00000012,
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regk_bif_core_bit19 = 0x00000013,
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regk_bif_core_bit20 = 0x00000014,
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regk_bif_core_bit21 = 0x00000015,
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regk_bif_core_bit22 = 0x00000016,
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regk_bif_core_bit23 = 0x00000017,
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regk_bif_core_bit24 = 0x00000018,
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regk_bif_core_bit25 = 0x00000019,
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regk_bif_core_bit26 = 0x0000001a,
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regk_bif_core_bit27 = 0x0000001b,
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regk_bif_core_bit28 = 0x0000001c,
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regk_bif_core_bit29 = 0x0000001d,
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regk_bif_core_bit9 = 0x00000009,
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regk_bif_core_bw16 = 0x00000001,
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regk_bif_core_bw32 = 0x00000000,
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regk_bif_core_bwe = 0x00000000,
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regk_bif_core_cwe = 0x00000001,
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regk_bif_core_e15us = 0x00000001,
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regk_bif_core_e7800ns = 0x00000002,
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regk_bif_core_grp0 = 0x00000000,
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regk_bif_core_grp1 = 0x00000001,
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regk_bif_core_mrs = 0x00000003,
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regk_bif_core_no = 0x00000000,
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regk_bif_core_none = 0x00000000,
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regk_bif_core_nop = 0x00000000,
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regk_bif_core_off = 0x00000000,
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regk_bif_core_pre = 0x00000002,
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regk_bif_core_r_sdram_ref_stat_default = 0x00000001,
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regk_bif_core_rd = 0x00000002,
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regk_bif_core_ref = 0x00000001,
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regk_bif_core_rs_sdram_ref_stat_default = 0x00000001,
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regk_bif_core_rw_grp1_cfg_default = 0x000006cf,
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regk_bif_core_rw_grp2_cfg_default = 0x000006cf,
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regk_bif_core_rw_grp3_cfg_default = 0x000006cf,
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regk_bif_core_rw_grp4_cfg_default = 0x000006cf,
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regk_bif_core_rw_sdram_cfg_grp1_default = 0x00000000,
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regk_bif_core_slf = 0x00000004,
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regk_bif_core_wr = 0x00000001,
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regk_bif_core_yes = 0x00000001
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};
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#endif /* __bif_core_defs_h */
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