Atsushi Nemoto d10e025f0e MIPS: TXx9: Cache fixup ... TX39/TX49 can enable/disable I/D cache at runtime. Add kernel options to control them. This is useful to debug some cache-related issues, such as aliasing or I/D coherency. Also enable CWF bit for TX49 SoCs. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>		2008-10-11 16:18:42 +01:00
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generic	MIPS: TXx9: Cache fixup	2008-10-11 16:18:42 +01:00
jmr3927	MIPS: TXx9: Cache fixup	2008-10-11 16:18:42 +01:00
rbtx4927	MIPS: TXx9: Cache fixup	2008-10-11 16:18:42 +01:00
rbtx4938	MIPS: TXx9: Improve handling of built-in and command-line args	2008-10-11 16:18:41 +01:00
Kconfig	MIPS: TXx9: Improve handling of built-in and command-line args	2008-10-11 16:18:41 +01:00