kernel-ark/include/dt-bindings/reset/sun9i-a80-de.h
Chen-Yu Tsai 783ab76ae5 clk: sunxi-ng: Add A80 Display Engine CCU
With the A80 SoC, Allwinner grouped and moved some subsystem specific
clock controls to a separate address space, and possibly separate
hardware block.

One such subsystem is the display engine. The main clock control unit
now only has 1 set of bus gate, dram gate, module clock, and reset
control for the entire display subsystem. These feed into a secondary
clock control unit, which has controls for each individual module
of the display pipeline. This block is not documented in the user
manual. Allwinner's kernel was used as the reference.

Add support for the display engine clock controls found on the A80.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-01-30 08:38:30 +01:00

59 lines
2.3 KiB
C

/*
* Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
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*/
#ifndef _DT_BINDINGS_RESET_SUN9I_A80_DE_H_
#define _DT_BINDINGS_RESET_SUN9I_A80_DE_H_
#define RST_FE0 0
#define RST_FE1 1
#define RST_FE2 2
#define RST_DEU0 3
#define RST_DEU1 4
#define RST_BE0 5
#define RST_BE1 6
#define RST_BE2 7
#define RST_DRC0 8
#define RST_DRC1 9
#define RST_MERGE 10
#endif /* _DT_BINDINGS_RESET_SUN9I_A80_DE_H_ */