a27e951f1e
Fix cyrix section references: convert __initdata to __devinitdata. Error: ./arch/i386/kernel/cpu/mtrr/cyrix.o .text refers to 00000379 R_386_32 .init.data Error: ./arch/i386/kernel/cpu/mtrr/cyrix.o .text refers to 00000399 R_386_32 .init.data Error: ./arch/i386/kernel/cpu/mtrr/cyrix.o .text refers to 000003b3 R_386_32 .init.data Error: ./arch/i386/kernel/cpu/mtrr/cyrix.o .text refers to 000003b9 R_386_32 .init.data Error: ./arch/i386/kernel/cpu/mtrr/cyrix.o .text refers to 000003bf R_386_32 .init.data Signed-of-by: maximilian attems <janitor@sternwelten.at> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
365 lines
8.5 KiB
C
365 lines
8.5 KiB
C
#include <linux/init.h>
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#include <linux/mm.h>
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#include <asm/mtrr.h>
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#include <asm/msr.h>
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#include <asm/io.h>
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#include "mtrr.h"
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int arr3_protected;
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static void
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cyrix_get_arr(unsigned int reg, unsigned long *base,
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unsigned int *size, mtrr_type * type)
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{
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unsigned long flags;
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unsigned char arr, ccr3, rcr, shift;
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arr = CX86_ARR_BASE + (reg << 1) + reg; /* avoid multiplication by 3 */
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/* Save flags and disable interrupts */
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local_irq_save(flags);
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ccr3 = getCx86(CX86_CCR3);
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setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */
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((unsigned char *) base)[3] = getCx86(arr);
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((unsigned char *) base)[2] = getCx86(arr + 1);
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((unsigned char *) base)[1] = getCx86(arr + 2);
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rcr = getCx86(CX86_RCR_BASE + reg);
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setCx86(CX86_CCR3, ccr3); /* disable MAPEN */
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/* Enable interrupts if it was enabled previously */
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local_irq_restore(flags);
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shift = ((unsigned char *) base)[1] & 0x0f;
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*base >>= PAGE_SHIFT;
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/* Power of two, at least 4K on ARR0-ARR6, 256K on ARR7
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* Note: shift==0xf means 4G, this is unsupported.
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*/
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if (shift)
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*size = (reg < 7 ? 0x1UL : 0x40UL) << (shift - 1);
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else
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*size = 0;
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/* Bit 0 is Cache Enable on ARR7, Cache Disable on ARR0-ARR6 */
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if (reg < 7) {
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switch (rcr) {
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case 1:
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*type = MTRR_TYPE_UNCACHABLE;
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break;
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case 8:
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*type = MTRR_TYPE_WRBACK;
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break;
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case 9:
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*type = MTRR_TYPE_WRCOMB;
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break;
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case 24:
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default:
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*type = MTRR_TYPE_WRTHROUGH;
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break;
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}
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} else {
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switch (rcr) {
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case 0:
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*type = MTRR_TYPE_UNCACHABLE;
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break;
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case 8:
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*type = MTRR_TYPE_WRCOMB;
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break;
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case 9:
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*type = MTRR_TYPE_WRBACK;
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break;
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case 25:
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default:
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*type = MTRR_TYPE_WRTHROUGH;
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break;
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}
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}
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}
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static int
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cyrix_get_free_region(unsigned long base, unsigned long size)
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/* [SUMMARY] Get a free ARR.
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<base> The starting (base) address of the region.
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<size> The size (in bytes) of the region.
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[RETURNS] The index of the region on success, else -1 on error.
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*/
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{
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int i;
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mtrr_type ltype;
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unsigned long lbase;
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unsigned int lsize;
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/* If we are to set up a region >32M then look at ARR7 immediately */
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if (size > 0x2000) {
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cyrix_get_arr(7, &lbase, &lsize, <ype);
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if (lsize == 0)
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return 7;
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/* Else try ARR0-ARR6 first */
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} else {
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for (i = 0; i < 7; i++) {
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cyrix_get_arr(i, &lbase, &lsize, <ype);
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if ((i == 3) && arr3_protected)
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continue;
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if (lsize == 0)
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return i;
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}
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/* ARR0-ARR6 isn't free, try ARR7 but its size must be at least 256K */
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cyrix_get_arr(i, &lbase, &lsize, <ype);
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if ((lsize == 0) && (size >= 0x40))
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return i;
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}
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return -ENOSPC;
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}
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static u32 cr4 = 0;
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static u32 ccr3;
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static void prepare_set(void)
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{
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u32 cr0;
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/* Save value of CR4 and clear Page Global Enable (bit 7) */
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if ( cpu_has_pge ) {
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cr4 = read_cr4();
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write_cr4(cr4 & (unsigned char) ~(1 << 7));
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}
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/* Disable and flush caches. Note that wbinvd flushes the TLBs as
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a side-effect */
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cr0 = read_cr0() | 0x40000000;
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wbinvd();
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write_cr0(cr0);
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wbinvd();
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/* Cyrix ARRs - everything else were excluded at the top */
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ccr3 = getCx86(CX86_CCR3);
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/* Cyrix ARRs - everything else were excluded at the top */
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setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10);
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}
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static void post_set(void)
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{
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/* Flush caches and TLBs */
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wbinvd();
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/* Cyrix ARRs - everything else was excluded at the top */
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setCx86(CX86_CCR3, ccr3);
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/* Enable caches */
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write_cr0(read_cr0() & 0xbfffffff);
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/* Restore value of CR4 */
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if ( cpu_has_pge )
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write_cr4(cr4);
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}
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static void cyrix_set_arr(unsigned int reg, unsigned long base,
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unsigned long size, mtrr_type type)
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{
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unsigned char arr, arr_type, arr_size;
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arr = CX86_ARR_BASE + (reg << 1) + reg; /* avoid multiplication by 3 */
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/* count down from 32M (ARR0-ARR6) or from 2G (ARR7) */
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if (reg >= 7)
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size >>= 6;
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size &= 0x7fff; /* make sure arr_size <= 14 */
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for (arr_size = 0; size; arr_size++, size >>= 1) ;
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if (reg < 7) {
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switch (type) {
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case MTRR_TYPE_UNCACHABLE:
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arr_type = 1;
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break;
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case MTRR_TYPE_WRCOMB:
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arr_type = 9;
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break;
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case MTRR_TYPE_WRTHROUGH:
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arr_type = 24;
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break;
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default:
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arr_type = 8;
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break;
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}
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} else {
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switch (type) {
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case MTRR_TYPE_UNCACHABLE:
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arr_type = 0;
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break;
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case MTRR_TYPE_WRCOMB:
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arr_type = 8;
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break;
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case MTRR_TYPE_WRTHROUGH:
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arr_type = 25;
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break;
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default:
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arr_type = 9;
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break;
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}
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}
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prepare_set();
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base <<= PAGE_SHIFT;
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setCx86(arr, ((unsigned char *) &base)[3]);
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setCx86(arr + 1, ((unsigned char *) &base)[2]);
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setCx86(arr + 2, (((unsigned char *) &base)[1]) | arr_size);
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setCx86(CX86_RCR_BASE + reg, arr_type);
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post_set();
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}
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typedef struct {
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unsigned long base;
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unsigned int size;
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mtrr_type type;
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} arr_state_t;
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static arr_state_t arr_state[8] __devinitdata = {
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{0UL, 0UL, 0UL}, {0UL, 0UL, 0UL}, {0UL, 0UL, 0UL}, {0UL, 0UL, 0UL},
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{0UL, 0UL, 0UL}, {0UL, 0UL, 0UL}, {0UL, 0UL, 0UL}, {0UL, 0UL, 0UL}
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};
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static unsigned char ccr_state[7] __devinitdata = { 0, 0, 0, 0, 0, 0, 0 };
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static void cyrix_set_all(void)
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{
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int i;
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prepare_set();
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/* the CCRs are not contiguous */
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for (i = 0; i < 4; i++)
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setCx86(CX86_CCR0 + i, ccr_state[i]);
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for (; i < 7; i++)
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setCx86(CX86_CCR4 + i, ccr_state[i]);
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for (i = 0; i < 8; i++)
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cyrix_set_arr(i, arr_state[i].base,
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arr_state[i].size, arr_state[i].type);
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post_set();
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}
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#if 0
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/*
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* On Cyrix 6x86(MX) and M II the ARR3 is special: it has connection
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* with the SMM (System Management Mode) mode. So we need the following:
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* Check whether SMI_LOCK (CCR3 bit 0) is set
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* if it is set, write a warning message: ARR3 cannot be changed!
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* (it cannot be changed until the next processor reset)
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* if it is reset, then we can change it, set all the needed bits:
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* - disable access to SMM memory through ARR3 range (CCR1 bit 7 reset)
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* - disable access to SMM memory (CCR1 bit 2 reset)
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* - disable SMM mode (CCR1 bit 1 reset)
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* - disable write protection of ARR3 (CCR6 bit 1 reset)
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* - (maybe) disable ARR3
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* Just to be sure, we enable ARR usage by the processor (CCR5 bit 5 set)
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*/
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static void __init
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cyrix_arr_init(void)
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{
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struct set_mtrr_context ctxt;
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unsigned char ccr[7];
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int ccrc[7] = { 0, 0, 0, 0, 0, 0, 0 };
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#ifdef CONFIG_SMP
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int i;
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#endif
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/* flush cache and enable MAPEN */
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set_mtrr_prepare_save(&ctxt);
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set_mtrr_cache_disable(&ctxt);
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/* Save all CCRs locally */
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ccr[0] = getCx86(CX86_CCR0);
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ccr[1] = getCx86(CX86_CCR1);
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ccr[2] = getCx86(CX86_CCR2);
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ccr[3] = ctxt.ccr3;
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ccr[4] = getCx86(CX86_CCR4);
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ccr[5] = getCx86(CX86_CCR5);
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ccr[6] = getCx86(CX86_CCR6);
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if (ccr[3] & 1) {
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ccrc[3] = 1;
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arr3_protected = 1;
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} else {
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/* Disable SMM mode (bit 1), access to SMM memory (bit 2) and
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* access to SMM memory through ARR3 (bit 7).
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*/
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if (ccr[1] & 0x80) {
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ccr[1] &= 0x7f;
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ccrc[1] |= 0x80;
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}
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if (ccr[1] & 0x04) {
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ccr[1] &= 0xfb;
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ccrc[1] |= 0x04;
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}
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if (ccr[1] & 0x02) {
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ccr[1] &= 0xfd;
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ccrc[1] |= 0x02;
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}
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arr3_protected = 0;
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if (ccr[6] & 0x02) {
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ccr[6] &= 0xfd;
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ccrc[6] = 1; /* Disable write protection of ARR3 */
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setCx86(CX86_CCR6, ccr[6]);
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}
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/* Disable ARR3. This is safe now that we disabled SMM. */
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/* cyrix_set_arr_up (3, 0, 0, 0, FALSE); */
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}
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/* If we changed CCR1 in memory, change it in the processor, too. */
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if (ccrc[1])
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setCx86(CX86_CCR1, ccr[1]);
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/* Enable ARR usage by the processor */
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if (!(ccr[5] & 0x20)) {
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ccr[5] |= 0x20;
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ccrc[5] = 1;
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setCx86(CX86_CCR5, ccr[5]);
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}
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#ifdef CONFIG_SMP
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for (i = 0; i < 7; i++)
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ccr_state[i] = ccr[i];
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for (i = 0; i < 8; i++)
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cyrix_get_arr(i,
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&arr_state[i].base, &arr_state[i].size,
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&arr_state[i].type);
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#endif
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set_mtrr_done(&ctxt); /* flush cache and disable MAPEN */
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if (ccrc[5])
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printk(KERN_INFO "mtrr: ARR usage was not enabled, enabled manually\n");
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if (ccrc[3])
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printk(KERN_INFO "mtrr: ARR3 cannot be changed\n");
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/*
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if ( ccrc[1] & 0x80) printk ("mtrr: SMM memory access through ARR3 disabled\n");
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if ( ccrc[1] & 0x04) printk ("mtrr: SMM memory access disabled\n");
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if ( ccrc[1] & 0x02) printk ("mtrr: SMM mode disabled\n");
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*/
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if (ccrc[6])
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printk(KERN_INFO "mtrr: ARR3 was write protected, unprotected\n");
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}
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#endif
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static struct mtrr_ops cyrix_mtrr_ops = {
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.vendor = X86_VENDOR_CYRIX,
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// .init = cyrix_arr_init,
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.set_all = cyrix_set_all,
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.set = cyrix_set_arr,
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.get = cyrix_get_arr,
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.get_free_region = cyrix_get_free_region,
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.validate_add_page = generic_validate_add_page,
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.have_wrcomb = positive_have_wrcomb,
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};
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int __init cyrix_init_mtrr(void)
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{
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set_mtrr_ops(&cyrix_mtrr_ops);
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return 0;
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}
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//arch_initcall(cyrix_init_mtrr);
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