cbf2829b61
Current APIC code assumes MSR_IA32_APICBASE is present for all systems. Pentium Classic P5 and friends didn't have this MSR. MSR_IA32_APICBASE was introduced as an architectural MSR by Intel @ P6. Code paths that can touch this MSR invalidly are when vendor == Intel && cpu-family == 5 and APIC bit is set in CPUID - or when you simply pass lapic on the kernel command line, on a P5. The below patch stops Linux incorrectly interfering with the MSR_IA32_APICBASE for P5 class machines. Other code paths exist that touch the MSR - however those paths are not currently reachable for a conformant P5. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linux.intel.com> Link: http://lkml.kernel.org/r/4F8EEDD3.1080404@linux.intel.com Signed-off-by: H. Peter Anvin <hpa@linux.intel.com> Cc: <stable@vger.kernel.org> |
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| .. | ||
| apic_flat_64.c | ||
| apic_noop.c | ||
| apic_numachip.c | ||
| apic.c | ||
| bigsmp_32.c | ||
| es7000_32.c | ||
| hw_nmi.c | ||
| io_apic.c | ||
| ipi.c | ||
| Makefile | ||
| numaq_32.c | ||
| probe_32.c | ||
| probe_64.c | ||
| summit_32.c | ||
| x2apic_cluster.c | ||
| x2apic_phys.c | ||
| x2apic_uv_x.c | ||