Suzuki K Poulose cd407abd5e coresight tmc etr: Cleanup AXICTL register handling ... This patch cleans up how we setup the AXICTL register on TMC ETR. At the moment we don't set the CacheCtrl bits, which drives the arcache and awcache bits on AXI bus specifying the cacheablitiy. Set this to Write-back Read and Write-allocate. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>		2017-08-28 16:05:49 +02:00
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coresight	coresight tmc etr: Cleanup AXICTL register handling	2017-08-28 16:05:49 +02:00
intel_th	hwtracing: intel_th: use dev_groups and not dev_attrs for bus_type	2017-06-09 11:00:46 +02:00
stm	This release has a few updates:	2016-12-15 13:49:34 -08:00