418 lines
10 KiB
C
418 lines
10 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2004-2008, 2009, 2010 Cavium Networks
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*/
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#include <linux/cpu.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/smp.h>
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#include <linux/interrupt.h>
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#include <linux/kernel_stat.h>
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#include <linux/sched.h>
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#include <linux/module.h>
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#include <asm/mmu_context.h>
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#include <asm/time.h>
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#include <asm/setup.h>
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#include <asm/octeon/octeon.h>
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#include "octeon_boot.h"
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volatile unsigned long octeon_processor_boot = 0xff;
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volatile unsigned long octeon_processor_sp;
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volatile unsigned long octeon_processor_gp;
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#ifdef CONFIG_HOTPLUG_CPU
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uint64_t octeon_bootloader_entry_addr;
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EXPORT_SYMBOL(octeon_bootloader_entry_addr);
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#endif
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static irqreturn_t mailbox_interrupt(int irq, void *dev_id)
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{
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const int coreid = cvmx_get_core_num();
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uint64_t action;
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/* Load the mailbox register to figure out what we're supposed to do */
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action = cvmx_read_csr(CVMX_CIU_MBOX_CLRX(coreid)) & 0xffff;
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/* Clear the mailbox to clear the interrupt */
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cvmx_write_csr(CVMX_CIU_MBOX_CLRX(coreid), action);
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if (action & SMP_CALL_FUNCTION)
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smp_call_function_interrupt();
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if (action & SMP_RESCHEDULE_YOURSELF)
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scheduler_ipi();
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/* Check if we've been told to flush the icache */
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if (action & SMP_ICACHE_FLUSH)
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asm volatile ("synci 0($0)\n");
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return IRQ_HANDLED;
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}
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/**
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* Cause the function described by call_data to be executed on the passed
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* cpu. When the function has finished, increment the finished field of
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* call_data.
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*/
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void octeon_send_ipi_single(int cpu, unsigned int action)
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{
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int coreid = cpu_logical_map(cpu);
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/*
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pr_info("SMP: Mailbox send cpu=%d, coreid=%d, action=%u\n", cpu,
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coreid, action);
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*/
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cvmx_write_csr(CVMX_CIU_MBOX_SETX(coreid), action);
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}
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static inline void octeon_send_ipi_mask(const struct cpumask *mask,
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unsigned int action)
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{
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unsigned int i;
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for_each_cpu_mask(i, *mask)
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octeon_send_ipi_single(i, action);
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}
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/**
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* Detect available CPUs, populate cpu_possible_mask
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*/
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static void octeon_smp_hotplug_setup(void)
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{
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#ifdef CONFIG_HOTPLUG_CPU
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struct linux_app_boot_info *labi;
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labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
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if (labi->labi_signature != LABI_SIGNATURE)
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panic("The bootloader version on this board is incorrect.");
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octeon_bootloader_entry_addr = labi->InitTLBStart_addr;
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#endif
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}
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static void octeon_smp_setup(void)
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{
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const int coreid = cvmx_get_core_num();
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int cpus;
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int id;
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int core_mask = octeon_get_boot_coremask();
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#ifdef CONFIG_HOTPLUG_CPU
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unsigned int num_cores = cvmx_octeon_num_cores();
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#endif
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/* The present CPUs are initially just the boot cpu (CPU 0). */
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for (id = 0; id < NR_CPUS; id++) {
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set_cpu_possible(id, id == 0);
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set_cpu_present(id, id == 0);
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}
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__cpu_number_map[coreid] = 0;
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__cpu_logical_map[0] = coreid;
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/* The present CPUs get the lowest CPU numbers. */
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cpus = 1;
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for (id = 0; id < NR_CPUS; id++) {
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if ((id != coreid) && (core_mask & (1 << id))) {
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set_cpu_possible(cpus, true);
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set_cpu_present(cpus, true);
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__cpu_number_map[id] = cpus;
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__cpu_logical_map[cpus] = id;
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cpus++;
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}
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}
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#ifdef CONFIG_HOTPLUG_CPU
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/*
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* The possible CPUs are all those present on the chip. We
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* will assign CPU numbers for possible cores as well. Cores
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* are always consecutively numberd from 0.
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*/
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for (id = 0; id < num_cores && id < NR_CPUS; id++) {
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if (!(core_mask & (1 << id))) {
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set_cpu_possible(cpus, true);
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__cpu_number_map[id] = cpus;
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__cpu_logical_map[cpus] = id;
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cpus++;
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}
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}
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#endif
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octeon_smp_hotplug_setup();
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}
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/**
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* Firmware CPU startup hook
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*
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*/
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static void octeon_boot_secondary(int cpu, struct task_struct *idle)
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{
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int count;
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pr_info("SMP: Booting CPU%02d (CoreId %2d)...\n", cpu,
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cpu_logical_map(cpu));
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octeon_processor_sp = __KSTK_TOS(idle);
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octeon_processor_gp = (unsigned long)(task_thread_info(idle));
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octeon_processor_boot = cpu_logical_map(cpu);
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mb();
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count = 10000;
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while (octeon_processor_sp && count) {
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/* Waiting for processor to get the SP and GP */
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udelay(1);
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count--;
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}
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if (count == 0)
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pr_err("Secondary boot timeout\n");
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}
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/**
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* After we've done initial boot, this function is called to allow the
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* board code to clean up state, if needed
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*/
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static void octeon_init_secondary(void)
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{
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unsigned int sr;
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sr = set_c0_status(ST0_BEV);
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write_c0_ebase((u32)ebase);
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write_c0_status(sr);
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octeon_check_cpu_bist();
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octeon_init_cvmcount();
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octeon_irq_setup_secondary();
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}
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/**
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* Callout to firmware before smp_init
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*
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*/
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void octeon_prepare_cpus(unsigned int max_cpus)
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{
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#ifdef CONFIG_HOTPLUG_CPU
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struct linux_app_boot_info *labi;
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labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
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if (labi->labi_signature != LABI_SIGNATURE)
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panic("The bootloader version on this board is incorrect.");
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#endif
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/*
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* Only the low order mailbox bits are used for IPIs, leave
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* the other bits alone.
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*/
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cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffff);
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if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt,
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IRQF_PERCPU | IRQF_NO_THREAD, "SMP-IPI",
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mailbox_interrupt)) {
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panic("Cannot request_irq(OCTEON_IRQ_MBOX0)");
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}
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}
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/**
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* Last chance for the board code to finish SMP initialization before
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* the CPU is "online".
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*/
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static void octeon_smp_finish(void)
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{
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#ifdef CONFIG_CAVIUM_GDB
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unsigned long tmp;
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/* Pulse MCD0 signal on Ctrl-C to stop all the cores. Also set the MCD0
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to be not masked by this core so we know the signal is received by
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someone */
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asm volatile ("dmfc0 %0, $22\n"
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"ori %0, %0, 0x9100\n" "dmtc0 %0, $22\n" : "=r" (tmp));
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#endif
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octeon_user_io_init();
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/* to generate the first CPU timer interrupt */
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write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
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local_irq_enable();
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}
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/**
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* Hook for after all CPUs are online
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*/
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static void octeon_cpus_done(void)
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{
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#ifdef CONFIG_CAVIUM_GDB
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unsigned long tmp;
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/* Pulse MCD0 signal on Ctrl-C to stop all the cores. Also set the MCD0
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to be not masked by this core so we know the signal is received by
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someone */
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asm volatile ("dmfc0 %0, $22\n"
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"ori %0, %0, 0x9100\n" "dmtc0 %0, $22\n" : "=r" (tmp));
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#endif
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}
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#ifdef CONFIG_HOTPLUG_CPU
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/* State of each CPU. */
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DEFINE_PER_CPU(int, cpu_state);
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static int octeon_cpu_disable(void)
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{
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unsigned int cpu = smp_processor_id();
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if (cpu == 0)
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return -EBUSY;
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set_cpu_online(cpu, false);
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cpu_clear(cpu, cpu_callin_map);
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local_irq_disable();
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octeon_fixup_irqs();
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local_irq_enable();
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flush_cache_all();
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local_flush_tlb_all();
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return 0;
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}
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static void octeon_cpu_die(unsigned int cpu)
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{
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int coreid = cpu_logical_map(cpu);
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uint32_t mask, new_mask;
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const struct cvmx_bootmem_named_block_desc *block_desc;
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while (per_cpu(cpu_state, cpu) != CPU_DEAD)
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cpu_relax();
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/*
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* This is a bit complicated strategics of getting/settig available
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* cores mask, copied from bootloader
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*/
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mask = 1 << coreid;
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/* LINUX_APP_BOOT_BLOCK is initialized in bootoct binary */
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block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME);
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if (!block_desc) {
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struct linux_app_boot_info *labi;
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labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
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labi->avail_coremask |= mask;
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new_mask = labi->avail_coremask;
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} else { /* alternative, already initialized */
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uint32_t *p = (uint32_t *)PHYS_TO_XKSEG_CACHED(block_desc->base_addr +
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AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK);
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*p |= mask;
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new_mask = *p;
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}
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pr_info("Reset core %d. Available Coremask = 0x%x \n", coreid, new_mask);
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mb();
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cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
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cvmx_write_csr(CVMX_CIU_PP_RST, 0);
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}
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void play_dead(void)
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{
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int cpu = cpu_number_map(cvmx_get_core_num());
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idle_task_exit();
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octeon_processor_boot = 0xff;
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per_cpu(cpu_state, cpu) = CPU_DEAD;
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mb();
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while (1) /* core will be reset here */
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;
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}
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extern void kernel_entry(unsigned long arg1, ...);
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static void start_after_reset(void)
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{
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kernel_entry(0, 0, 0); /* set a2 = 0 for secondary core */
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}
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static int octeon_update_boot_vector(unsigned int cpu)
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{
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int coreid = cpu_logical_map(cpu);
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uint32_t avail_coremask;
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const struct cvmx_bootmem_named_block_desc *block_desc;
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struct boot_init_vector *boot_vect =
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(struct boot_init_vector *)PHYS_TO_XKSEG_CACHED(BOOTLOADER_BOOT_VECTOR);
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block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME);
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if (!block_desc) {
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struct linux_app_boot_info *labi;
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labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
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avail_coremask = labi->avail_coremask;
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labi->avail_coremask &= ~(1 << coreid);
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} else { /* alternative, already initialized */
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avail_coremask = *(uint32_t *)PHYS_TO_XKSEG_CACHED(
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block_desc->base_addr + AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK);
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}
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if (!(avail_coremask & (1 << coreid))) {
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/* core not available, assume, that catched by simple-executive */
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cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
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cvmx_write_csr(CVMX_CIU_PP_RST, 0);
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}
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boot_vect[coreid].app_start_func_addr =
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(uint32_t) (unsigned long) start_after_reset;
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boot_vect[coreid].code_addr = octeon_bootloader_entry_addr;
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mb();
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cvmx_write_csr(CVMX_CIU_NMI, (1 << coreid) & avail_coremask);
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return 0;
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}
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static int octeon_cpu_callback(struct notifier_block *nfb,
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unsigned long action, void *hcpu)
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{
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unsigned int cpu = (unsigned long)hcpu;
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switch (action) {
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case CPU_UP_PREPARE:
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octeon_update_boot_vector(cpu);
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break;
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case CPU_ONLINE:
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pr_info("Cpu %d online\n", cpu);
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break;
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case CPU_DEAD:
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break;
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}
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return NOTIFY_OK;
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}
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static int register_cavium_notifier(void)
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{
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hotcpu_notifier(octeon_cpu_callback, 0);
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return 0;
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}
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late_initcall(register_cavium_notifier);
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#endif /* CONFIG_HOTPLUG_CPU */
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struct plat_smp_ops octeon_smp_ops = {
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.send_ipi_single = octeon_send_ipi_single,
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.send_ipi_mask = octeon_send_ipi_mask,
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.init_secondary = octeon_init_secondary,
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.smp_finish = octeon_smp_finish,
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.cpus_done = octeon_cpus_done,
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.boot_secondary = octeon_boot_secondary,
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.smp_setup = octeon_smp_setup,
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.prepare_cpus = octeon_prepare_cpus,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_disable = octeon_cpu_disable,
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.cpu_die = octeon_cpu_die,
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#endif
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};
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