7cc4e87f91
* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (236 commits)
[ARM] 5300/1: fixup spitz reset during boot
[ARM] 5295/1: make ZONE_DMA optional
[ARM] 5239/1: Palm Zire 72 power management support
[ARM] 5298/1: Drop desc_handle_irq()
[ARM] 5297/1: [KS8695] Fix two compile-time warnings
[ARM] 5296/1: [KS8695] Replace macro's with trailing underscores.
[ARM] pxa: allow multi-machine PCMCIA builds
[ARM] pxa: add preliminary CPUFREQ support for PXA3xx
[ARM] pxa: add missing ACCR bit definitions to pxa3xx-regs.h
[ARM] pxa: rename cpu-pxa.c to cpufreq-pxa2xx.c
[ARM] pxa/zylonite: add support for USB OHCI
[ARM] ohci-pxa27x: use ioremap() and offset for register access
[ARM] ohci-pxa27x: introduce pxa27x_clear_otgph()
[ARM] ohci-pxa27x: use platform_get_{irq,resource} for the resource
[ARM] ohci-pxa27x: move OHCI controller specific registers into the driver
[ARM] ohci-pxa27x: introduce flags to avoid direct access to OHCI registers
[ARM] pxa: move I2S register and bit definitions into pxa2xx-i2s.c
[ARM] pxa: simplify DMA register definitions
[ARM] pxa: make additional DCSR bits valid for PXA3xx
[ARM] pxa: move i2c register and bit definitions into i2c-pxa.c
...
Fixed up conflicts in
arch/arm/mach-versatile/core.c
sound/soc/pxa/pxa2xx-ac97.c
sound/soc/pxa/pxa2xx-i2s.c
manually.
461 lines
10 KiB
C
461 lines
10 KiB
C
/*
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* linux/arch/arm/mach-sa1100/generic.c
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*
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* Author: Nicolas Pitre
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*
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* Code common to all SA11x0 machines.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/pm.h>
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#include <linux/cpufreq.h>
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#include <linux/ioport.h>
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#include <linux/sched.h> /* just for sched_clock() - funny that */
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#include <linux/platform_device.h>
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#include <linux/cnt32_to_63.h>
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#include <asm/div64.h>
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#include <mach/hardware.h>
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#include <asm/system.h>
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#include <asm/pgtable.h>
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#include <asm/mach/map.h>
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#include <asm/mach/flash.h>
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#include <asm/irq.h>
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#include <asm/gpio.h>
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#include "generic.h"
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unsigned int reset_status;
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EXPORT_SYMBOL(reset_status);
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#define NR_FREQS 16
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/*
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* This table is setup for a 3.6864MHz Crystal.
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*/
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static const unsigned short cclk_frequency_100khz[NR_FREQS] = {
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590, /* 59.0 MHz */
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737, /* 73.7 MHz */
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885, /* 88.5 MHz */
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1032, /* 103.2 MHz */
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1180, /* 118.0 MHz */
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1327, /* 132.7 MHz */
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1475, /* 147.5 MHz */
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1622, /* 162.2 MHz */
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1769, /* 176.9 MHz */
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1917, /* 191.7 MHz */
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2064, /* 206.4 MHz */
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2212, /* 221.2 MHz */
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2359, /* 235.9 MHz */
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2507, /* 250.7 MHz */
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2654, /* 265.4 MHz */
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2802 /* 280.2 MHz */
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};
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#if defined(CONFIG_CPU_FREQ_SA1100) || defined(CONFIG_CPU_FREQ_SA1110)
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/* rounds up(!) */
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unsigned int sa11x0_freq_to_ppcr(unsigned int khz)
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{
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int i;
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khz /= 100;
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for (i = 0; i < NR_FREQS; i++)
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if (cclk_frequency_100khz[i] >= khz)
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break;
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return i;
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}
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unsigned int sa11x0_ppcr_to_freq(unsigned int idx)
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{
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unsigned int freq = 0;
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if (idx < NR_FREQS)
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freq = cclk_frequency_100khz[idx] * 100;
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return freq;
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}
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/* make sure that only the "userspace" governor is run -- anything else wouldn't make sense on
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* this platform, anyway.
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*/
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int sa11x0_verify_speed(struct cpufreq_policy *policy)
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{
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unsigned int tmp;
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if (policy->cpu)
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return -EINVAL;
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cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, policy->cpuinfo.max_freq);
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/* make sure that at least one frequency is within the policy */
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tmp = cclk_frequency_100khz[sa11x0_freq_to_ppcr(policy->min)] * 100;
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if (tmp > policy->max)
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policy->max = tmp;
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cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, policy->cpuinfo.max_freq);
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return 0;
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}
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unsigned int sa11x0_getspeed(unsigned int cpu)
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{
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if (cpu)
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return 0;
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return cclk_frequency_100khz[PPCR & 0xf] * 100;
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}
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#else
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/*
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* We still need to provide this so building without cpufreq works.
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*/
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unsigned int cpufreq_get(unsigned int cpu)
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{
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return cclk_frequency_100khz[PPCR & 0xf] * 100;
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}
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EXPORT_SYMBOL(cpufreq_get);
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#endif
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/*
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* This is the SA11x0 sched_clock implementation. This has
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* a resolution of 271ns, and a maximum value of 32025597s (370 days).
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*
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* The return value is guaranteed to be monotonic in that range as
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* long as there is always less than 582 seconds between successive
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* calls to this function.
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*
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* ( * 1E9 / 3686400 => * 78125 / 288)
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*/
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unsigned long long sched_clock(void)
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{
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unsigned long long v = cnt32_to_63(OSCR);
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/* the <<1 gets rid of the cnt_32_to_63 top bit saving on a bic insn */
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v *= 78125<<1;
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do_div(v, 288<<1);
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return v;
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}
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/*
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* Default power-off for SA1100
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*/
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static void sa1100_power_off(void)
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{
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mdelay(100);
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local_irq_disable();
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/* disable internal oscillator, float CS lines */
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PCFR = (PCFR_OPDE | PCFR_FP | PCFR_FS);
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/* enable wake-up on GPIO0 (Assabet...) */
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PWER = GFER = GRER = 1;
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/*
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* set scratchpad to zero, just in case it is used as a
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* restart address by the bootloader.
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*/
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PSPR = 0;
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/* enter sleep mode */
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PMCR = PMCR_SF;
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}
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static struct resource sa11x0udc_resources[] = {
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[0] = {
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.start = 0x80000000,
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.end = 0x8000ffff,
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.flags = IORESOURCE_MEM,
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},
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};
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static u64 sa11x0udc_dma_mask = 0xffffffffUL;
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static struct platform_device sa11x0udc_device = {
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.name = "sa11x0-udc",
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.id = -1,
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.dev = {
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.dma_mask = &sa11x0udc_dma_mask,
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.coherent_dma_mask = 0xffffffff,
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},
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.num_resources = ARRAY_SIZE(sa11x0udc_resources),
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.resource = sa11x0udc_resources,
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};
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static struct resource sa11x0uart1_resources[] = {
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[0] = {
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.start = 0x80010000,
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.end = 0x8001ffff,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device sa11x0uart1_device = {
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.name = "sa11x0-uart",
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.id = 1,
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.num_resources = ARRAY_SIZE(sa11x0uart1_resources),
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.resource = sa11x0uart1_resources,
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};
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static struct resource sa11x0uart3_resources[] = {
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[0] = {
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.start = 0x80050000,
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.end = 0x8005ffff,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device sa11x0uart3_device = {
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.name = "sa11x0-uart",
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.id = 3,
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.num_resources = ARRAY_SIZE(sa11x0uart3_resources),
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.resource = sa11x0uart3_resources,
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};
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static struct resource sa11x0mcp_resources[] = {
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[0] = {
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.start = 0x80060000,
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.end = 0x8006ffff,
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.flags = IORESOURCE_MEM,
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},
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};
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static u64 sa11x0mcp_dma_mask = 0xffffffffUL;
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static struct platform_device sa11x0mcp_device = {
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.name = "sa11x0-mcp",
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.id = -1,
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.dev = {
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.dma_mask = &sa11x0mcp_dma_mask,
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.coherent_dma_mask = 0xffffffff,
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},
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.num_resources = ARRAY_SIZE(sa11x0mcp_resources),
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.resource = sa11x0mcp_resources,
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};
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void sa11x0_set_mcp_data(struct mcp_plat_data *data)
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{
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sa11x0mcp_device.dev.platform_data = data;
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}
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static struct resource sa11x0ssp_resources[] = {
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[0] = {
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.start = 0x80070000,
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.end = 0x8007ffff,
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.flags = IORESOURCE_MEM,
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},
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};
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static u64 sa11x0ssp_dma_mask = 0xffffffffUL;
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static struct platform_device sa11x0ssp_device = {
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.name = "sa11x0-ssp",
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.id = -1,
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.dev = {
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.dma_mask = &sa11x0ssp_dma_mask,
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.coherent_dma_mask = 0xffffffff,
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},
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.num_resources = ARRAY_SIZE(sa11x0ssp_resources),
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.resource = sa11x0ssp_resources,
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};
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static struct resource sa11x0fb_resources[] = {
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[0] = {
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.start = 0xb0100000,
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.end = 0xb010ffff,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_LCD,
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.end = IRQ_LCD,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device sa11x0fb_device = {
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.name = "sa11x0-fb",
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.id = -1,
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.dev = {
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.coherent_dma_mask = 0xffffffff,
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},
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.num_resources = ARRAY_SIZE(sa11x0fb_resources),
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.resource = sa11x0fb_resources,
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};
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static struct platform_device sa11x0pcmcia_device = {
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.name = "sa11x0-pcmcia",
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.id = -1,
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};
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static struct platform_device sa11x0mtd_device = {
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.name = "flash",
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.id = -1,
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};
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void sa11x0_set_flash_data(struct flash_platform_data *flash,
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struct resource *res, int nr)
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{
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flash->name = "sa1100";
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sa11x0mtd_device.dev.platform_data = flash;
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sa11x0mtd_device.resource = res;
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sa11x0mtd_device.num_resources = nr;
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}
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static struct resource sa11x0ir_resources[] = {
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{
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.start = __PREG(Ser2UTCR0),
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.end = __PREG(Ser2UTCR0) + 0x24 - 1,
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.flags = IORESOURCE_MEM,
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}, {
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.start = __PREG(Ser2HSCR0),
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.end = __PREG(Ser2HSCR0) + 0x1c - 1,
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.flags = IORESOURCE_MEM,
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}, {
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.start = __PREG(Ser2HSCR2),
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.end = __PREG(Ser2HSCR2) + 0x04 - 1,
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.flags = IORESOURCE_MEM,
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}, {
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.start = IRQ_Ser2ICP,
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.end = IRQ_Ser2ICP,
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.flags = IORESOURCE_IRQ,
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}
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};
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static struct platform_device sa11x0ir_device = {
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.name = "sa11x0-ir",
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.id = -1,
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.num_resources = ARRAY_SIZE(sa11x0ir_resources),
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.resource = sa11x0ir_resources,
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};
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void sa11x0_set_irda_data(struct irda_platform_data *irda)
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{
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sa11x0ir_device.dev.platform_data = irda;
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}
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static struct platform_device sa11x0rtc_device = {
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.name = "sa1100-rtc",
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.id = -1,
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};
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static struct platform_device *sa11x0_devices[] __initdata = {
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&sa11x0udc_device,
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&sa11x0uart1_device,
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&sa11x0uart3_device,
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&sa11x0mcp_device,
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&sa11x0ssp_device,
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&sa11x0pcmcia_device,
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&sa11x0fb_device,
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&sa11x0mtd_device,
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&sa11x0rtc_device,
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};
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static int __init sa1100_init(void)
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{
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pm_power_off = sa1100_power_off;
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if (sa11x0ir_device.dev.platform_data)
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platform_device_register(&sa11x0ir_device);
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return platform_add_devices(sa11x0_devices, ARRAY_SIZE(sa11x0_devices));
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}
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arch_initcall(sa1100_init);
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void (*sa1100fb_backlight_power)(int on);
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void (*sa1100fb_lcd_power)(int on);
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EXPORT_SYMBOL(sa1100fb_backlight_power);
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EXPORT_SYMBOL(sa1100fb_lcd_power);
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/*
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* Common I/O mapping:
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*
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* Typically, static virtual address mappings are as follow:
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*
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* 0xf0000000-0xf3ffffff: miscellaneous stuff (CPLDs, etc.)
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* 0xf4000000-0xf4ffffff: SA-1111
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* 0xf5000000-0xf5ffffff: reserved (used by cache flushing area)
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* 0xf6000000-0xfffeffff: reserved (internal SA1100 IO defined above)
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* 0xffff0000-0xffff0fff: SA1100 exception vectors
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* 0xffff2000-0xffff2fff: Minicache copy_user_page area
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*
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* Below 0xe8000000 is reserved for vm allocation.
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*
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* The machine specific code must provide the extra mapping beside the
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* default mapping provided here.
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*/
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static struct map_desc standard_io_desc[] __initdata = {
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{ /* PCM */
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.virtual = 0xf8000000,
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.pfn = __phys_to_pfn(0x80000000),
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.length = 0x00100000,
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.type = MT_DEVICE
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}, { /* SCM */
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.virtual = 0xfa000000,
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.pfn = __phys_to_pfn(0x90000000),
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.length = 0x00100000,
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.type = MT_DEVICE
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}, { /* MER */
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.virtual = 0xfc000000,
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.pfn = __phys_to_pfn(0xa0000000),
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.length = 0x00100000,
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.type = MT_DEVICE
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}, { /* LCD + DMA */
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.virtual = 0xfe000000,
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.pfn = __phys_to_pfn(0xb0000000),
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.length = 0x00200000,
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.type = MT_DEVICE
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},
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};
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void __init sa1100_map_io(void)
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{
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iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
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}
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/*
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* Disable the memory bus request/grant signals on the SA1110 to
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* ensure that we don't receive spurious memory requests. We set
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* the MBGNT signal false to ensure the SA1111 doesn't own the
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* SDRAM bus.
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*/
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void __init sa1110_mb_disable(void)
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{
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unsigned long flags;
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local_irq_save(flags);
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PGSR &= ~GPIO_MBGNT;
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GPCR = GPIO_MBGNT;
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GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT;
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GAFR &= ~(GPIO_MBGNT | GPIO_MBREQ);
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local_irq_restore(flags);
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}
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/*
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* If the system is going to use the SA-1111 DMA engines, set up
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* the memory bus request/grant pins.
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*/
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void __devinit sa1110_mb_enable(void)
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{
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unsigned long flags;
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local_irq_save(flags);
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PGSR &= ~GPIO_MBGNT;
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GPCR = GPIO_MBGNT;
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GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT;
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GAFR |= (GPIO_MBGNT | GPIO_MBREQ);
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TUCR |= TUCR_MR;
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local_irq_restore(flags);
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}
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