kernel-ark/arch/xtensa/kernel
Chris Zankel c50842df47 xtensa: add support for TLS
The Xtensa architecture provides a global register called THREADPTR
for the purpose of Thread Local Storage (TLS) support. This allows us
to use a fairly simple implementation, keeping the thread pointer in
the regset and simply saving and restoring it upon entering/exiting
the from user space.

Signed-off-by: Chris Zankel <chris@zankel.net>
2013-02-23 19:35:57 -08:00
..
align.S xtensa: clean up files to make them code-style compliant 2012-12-18 21:10:25 -08:00
asm-offsets.c xtensa: add support for TLS 2013-02-23 19:35:57 -08:00
coprocessor.S xtensa: clean up files to make them code-style compliant 2012-12-18 21:10:25 -08:00
entry.S xtensa: add support for TLS 2013-02-23 19:35:57 -08:00
head.S xtensa: dispatch medium-priority interrupts 2013-02-23 19:12:52 -08:00
irq.c xtensa: add device trees support 2012-12-18 21:10:23 -08:00
Makefile xtensa: clean up files to make them code-style compliant 2012-12-18 21:10:25 -08:00
module.c xtensa: clean up files to make them code-style compliant 2012-12-18 21:10:25 -08:00
pci-dma.c xtensa: add missing symbol exports 2012-10-03 15:12:52 -07:00
pci.c Xtensa patchset for 3.7 2012-10-09 16:11:46 +09:00
platform.c xtensa: clean up files to make them code-style compliant 2012-12-18 21:10:25 -08:00
process.c xtensa: add support for TLS 2013-02-23 19:35:57 -08:00
ptrace.c xtensa: add support for TLS 2013-02-23 19:35:57 -08:00
setup.c xtensa: dispatch medium-priority interrupts 2013-02-23 19:12:52 -08:00
signal.c xtensa: add support for TLS 2013-02-23 19:35:57 -08:00
syscall.c xtensa: avoid mmap cache aliasing 2013-02-23 19:12:53 -08:00
time.c xtensa: add IRQ domains support 2012-12-18 21:10:23 -08:00
traps.c xtensa: move spill_registers to traps.h 2013-02-23 19:22:48 -08:00
vectors.S xtensa: dispatch medium-priority interrupts 2013-02-23 19:12:52 -08:00
vmlinux.lds.S xtensa: dispatch medium-priority interrupts 2013-02-23 19:12:52 -08:00
xtensa_ksyms.c xtensa: switch to generic kernel_thread() 2012-10-25 15:00:03 -07:00