c2f6118a30
Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
701 lines
22 KiB
C
701 lines
22 KiB
C
/*
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* Agere Systems Inc.
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* 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
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*
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* Copyright © 2005 Agere Systems Inc.
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* All rights reserved.
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* http://www.agere.com
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*
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*------------------------------------------------------------------------------
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*
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* et1310_mac.c - All code and routines pertaining to the MAC
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*
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*------------------------------------------------------------------------------
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*
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* SOFTWARE LICENSE
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*
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* This software is provided subject to the following terms and conditions,
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* which you should read carefully before using the software. Using this
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* software indicates your acceptance of these terms and conditions. If you do
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* not agree with these terms and conditions, do not use the software.
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*
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* Copyright © 2005 Agere Systems Inc.
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* All rights reserved.
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*
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* Redistribution and use in source or binary forms, with or without
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* modifications, are permitted provided that the following conditions are met:
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*
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* . Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following Disclaimer as comments in the code as
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* well as in the documentation and/or other materials provided with the
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* distribution.
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*
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* . Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following Disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* . Neither the name of Agere Systems Inc. nor the names of the contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* Disclaimer
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*
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* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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* INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
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* USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
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* RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
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* DAMAGE.
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*
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*/
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#include "et131x_version.h"
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#include "et131x_defs.h"
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/ptrace.h>
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#include <linux/slab.h>
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#include <linux/ctype.h>
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#include <linux/string.h>
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#include <linux/timer.h>
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#include <linux/interrupt.h>
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#include <linux/in.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/bitops.h>
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#include <linux/pci.h>
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#include <asm/system.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/skbuff.h>
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#include <linux/if_arp.h>
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#include <linux/ioport.h>
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#include <linux/crc32.h>
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#include "et1310_phy.h"
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#include "et1310_pm.h"
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#include "et1310_jagcore.h"
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#include "et1310_mac.h"
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#include "et131x_adapter.h"
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#include "et131x_initpci.h"
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/**
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* ConfigMacRegs1 - Initialize the first part of MAC regs
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* @pAdpater: pointer to our adapter structure
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*/
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void ConfigMACRegs1(struct et131x_adapter *etdev)
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{
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struct _MAC_t __iomem *pMac = &etdev->regs->mac;
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MAC_STATION_ADDR1_t station1;
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MAC_STATION_ADDR2_t station2;
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u32 ipg;
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MII_MGMT_CFG_t mii_mgmt_cfg;
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/* First we need to reset everything. Write to MAC configuration
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* register 1 to perform reset.
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*/
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writel(0xC00F0000, &pMac->cfg1.value);
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/* Next lets configure the MAC Inter-packet gap register */
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ipg = 0x38005860; /* IPG1 0x38 IPG2 0x58 B2B 0x60 */
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ipg |= 0x50 << 8; /* ifg enforce 0x50 */
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writel(ipg, &pMac->ipg);
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/* Next lets configure the MAC Half Duplex register */
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/* BEB trunc 0xA, Ex Defer, Rexmit 0xF Coll 0x37 */
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writel(0x00A1F037, &pMac->hfdp);
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/* Next lets configure the MAC Interface Control register */
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writel(0, &pMac->if_ctrl.value);
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/* Let's move on to setting up the mii management configuration */
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mii_mgmt_cfg.bits.reset_mii_mgmt = 0;
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mii_mgmt_cfg.bits.scan_auto_incremt = 0;
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mii_mgmt_cfg.bits.preamble_suppress = 0;
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mii_mgmt_cfg.bits.mgmt_clk_reset = 0x7;
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writel(mii_mgmt_cfg.value, &pMac->mii_mgmt_cfg.value);
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/* Next lets configure the MAC Station Address register. These
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* values are read from the EEPROM during initialization and stored
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* in the adapter structure. We write what is stored in the adapter
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* structure to the MAC Station Address registers high and low. This
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* station address is used for generating and checking pause control
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* packets.
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*/
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station2.bits.Octet1 = etdev->CurrentAddress[0];
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station2.bits.Octet2 = etdev->CurrentAddress[1];
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station1.bits.Octet3 = etdev->CurrentAddress[2];
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station1.bits.Octet4 = etdev->CurrentAddress[3];
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station1.bits.Octet5 = etdev->CurrentAddress[4];
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station1.bits.Octet6 = etdev->CurrentAddress[5];
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writel(station1.value, &pMac->station_addr_1.value);
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writel(station2.value, &pMac->station_addr_2.value);
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/* Max ethernet packet in bytes that will passed by the mac without
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* being truncated. Allow the MAC to pass 4 more than our max packet
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* size. This is 4 for the Ethernet CRC.
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*
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* Packets larger than (RegistryJumboPacket) that do not contain a
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* VLAN ID will be dropped by the Rx function.
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*/
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writel(etdev->RegistryJumboPacket + 4, &pMac->max_fm_len.value);
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/* clear out MAC config reset */
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writel(0, &pMac->cfg1.value);
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}
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/**
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* ConfigMacRegs2 - Initialize the second part of MAC regs
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* @pAdpater: pointer to our adapter structure
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*/
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void ConfigMACRegs2(struct et131x_adapter *etdev)
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{
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int32_t delay = 0;
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struct _MAC_t __iomem *pMac = &etdev->regs->mac;
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MAC_CFG1_t cfg1;
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MAC_CFG2_t cfg2;
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MAC_IF_CTRL_t ifctrl;
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TXMAC_CTL_t ctl;
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ctl.value = readl(&etdev->regs->txmac.ctl.value);
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cfg1.value = readl(&pMac->cfg1.value);
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cfg2.value = readl(&pMac->cfg2.value);
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ifctrl.value = readl(&pMac->if_ctrl.value);
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if (etdev->linkspeed == TRUEPHY_SPEED_1000MBPS) {
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cfg2.bits.if_mode = 0x2;
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ifctrl.bits.phy_mode = 0x0;
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} else {
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cfg2.bits.if_mode = 0x1;
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ifctrl.bits.phy_mode = 0x1;
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}
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/* We need to enable Rx/Tx */
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cfg1.bits.rx_enable = 0x1;
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cfg1.bits.tx_enable = 0x1;
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/* Set up flow control */
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cfg1.bits.tx_flow = 0x1;
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if ((etdev->FlowControl == RxOnly) ||
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(etdev->FlowControl == Both)) {
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cfg1.bits.rx_flow = 0x1;
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} else {
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cfg1.bits.rx_flow = 0x0;
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}
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/* Initialize loop back to off */
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cfg1.bits.loop_back = 0;
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writel(cfg1.value, &pMac->cfg1.value);
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/* Now we need to initialize the MAC Configuration 2 register */
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cfg2.bits.preamble_len = 0x7;
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cfg2.bits.huge_frame = 0x0;
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/* LENGTH FIELD CHECKING bit4: Set this bit to cause the MAC to check
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* the frame's length field to ensure it matches the actual data
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* field length. Clear this bit if no length field checking is
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* desired. Its default is 0.
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*/
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cfg2.bits.len_check = 0x1;
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cfg2.bits.pad_crc = 0x1;
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cfg2.bits.crc_enable = 0x1;
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/* 1 - full duplex, 0 - half-duplex */
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cfg2.bits.full_duplex = etdev->duplex_mode;
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ifctrl.bits.ghd_mode = !etdev->duplex_mode;
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writel(ifctrl.value, &pMac->if_ctrl.value);
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writel(cfg2.value, &pMac->cfg2.value);
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do {
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udelay(10);
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delay++;
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cfg1.value = readl(&pMac->cfg1.value);
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} while ((!cfg1.bits.syncd_rx_en || !cfg1.bits.syncd_tx_en) &&
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delay < 100);
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if (delay == 100) {
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dev_warn(&etdev->pdev->dev,
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"Syncd bits did not respond correctly cfg1 word 0x%08x\n",
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cfg1.value);
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}
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/* Enable TXMAC */
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ctl.bits.txmac_en = 0x1;
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ctl.bits.fc_disable = 0x1;
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writel(ctl.value, &etdev->regs->txmac.ctl.value);
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/* Ready to start the RXDMA/TXDMA engine */
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if (etdev->Flags & fMP_ADAPTER_LOWER_POWER) {
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et131x_rx_dma_enable(etdev);
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et131x_tx_dma_enable(etdev);
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}
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}
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void ConfigRxMacRegs(struct et131x_adapter *etdev)
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{
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struct _RXMAC_t __iomem *pRxMac = &etdev->regs->rxmac;
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RXMAC_WOL_SA_LO_t sa_lo;
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RXMAC_WOL_SA_HI_t sa_hi;
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RXMAC_PF_CTRL_t pf_ctrl = { 0 };
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/* Disable the MAC while it is being configured (also disable WOL) */
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writel(0x8, &pRxMac->ctrl.value);
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/* Initialize WOL to disabled. */
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writel(0, &pRxMac->crc0.value);
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writel(0, &pRxMac->crc12.value);
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writel(0, &pRxMac->crc34.value);
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/* We need to set the WOL mask0 - mask4 next. We initialize it to
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* its default Values of 0x00000000 because there are not WOL masks
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* as of this time.
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*/
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writel(0, &pRxMac->mask0_word0);
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writel(0, &pRxMac->mask0_word1);
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writel(0, &pRxMac->mask0_word2);
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writel(0, &pRxMac->mask0_word3);
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writel(0, &pRxMac->mask1_word0);
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writel(0, &pRxMac->mask1_word1);
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writel(0, &pRxMac->mask1_word2);
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writel(0, &pRxMac->mask1_word3);
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writel(0, &pRxMac->mask2_word0);
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writel(0, &pRxMac->mask2_word1);
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writel(0, &pRxMac->mask2_word2);
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writel(0, &pRxMac->mask2_word3);
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writel(0, &pRxMac->mask3_word0);
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writel(0, &pRxMac->mask3_word1);
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writel(0, &pRxMac->mask3_word2);
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writel(0, &pRxMac->mask3_word3);
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writel(0, &pRxMac->mask4_word0);
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writel(0, &pRxMac->mask4_word1);
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writel(0, &pRxMac->mask4_word2);
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writel(0, &pRxMac->mask4_word3);
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/* Lets setup the WOL Source Address */
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sa_lo.bits.sa3 = etdev->CurrentAddress[2];
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sa_lo.bits.sa4 = etdev->CurrentAddress[3];
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sa_lo.bits.sa5 = etdev->CurrentAddress[4];
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sa_lo.bits.sa6 = etdev->CurrentAddress[5];
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writel(sa_lo.value, &pRxMac->sa_lo.value);
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sa_hi.bits.sa1 = etdev->CurrentAddress[0];
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sa_hi.bits.sa2 = etdev->CurrentAddress[1];
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writel(sa_hi.value, &pRxMac->sa_hi.value);
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/* Disable all Packet Filtering */
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writel(0, &pRxMac->pf_ctrl.value);
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/* Let's initialize the Unicast Packet filtering address */
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if (etdev->PacketFilter & ET131X_PACKET_TYPE_DIRECTED) {
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SetupDeviceForUnicast(etdev);
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pf_ctrl.bits.filter_uni_en = 1;
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} else {
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writel(0, &pRxMac->uni_pf_addr1.value);
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writel(0, &pRxMac->uni_pf_addr2.value);
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writel(0, &pRxMac->uni_pf_addr3.value);
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}
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/* Let's initialize the Multicast hash */
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if (etdev->PacketFilter & ET131X_PACKET_TYPE_ALL_MULTICAST) {
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pf_ctrl.bits.filter_multi_en = 0;
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} else {
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pf_ctrl.bits.filter_multi_en = 1;
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SetupDeviceForMulticast(etdev);
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}
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/* Runt packet filtering. Didn't work in version A silicon. */
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pf_ctrl.bits.min_pkt_size = NIC_MIN_PACKET_SIZE + 4;
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pf_ctrl.bits.filter_frag_en = 1;
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if (etdev->RegistryJumboPacket > 8192) {
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RXMAC_MCIF_CTRL_MAX_SEG_t mcif_ctrl_max_seg;
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/* In order to transmit jumbo packets greater than 8k, the
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* FIFO between RxMAC and RxDMA needs to be reduced in size
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* to (16k - Jumbo packet size). In order to implement this,
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* we must use "cut through" mode in the RxMAC, which chops
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* packets down into segments which are (max_size * 16). In
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* this case we selected 256 bytes, since this is the size of
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* the PCI-Express TLP's that the 1310 uses.
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*/
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mcif_ctrl_max_seg.bits.seg_en = 0x1;
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mcif_ctrl_max_seg.bits.fc_en = 0x0;
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mcif_ctrl_max_seg.bits.max_size = 0x10;
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writel(mcif_ctrl_max_seg.value,
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&pRxMac->mcif_ctrl_max_seg.value);
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} else {
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writel(0, &pRxMac->mcif_ctrl_max_seg.value);
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}
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/* Initialize the MCIF water marks */
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writel(0, &pRxMac->mcif_water_mark.value);
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/* Initialize the MIF control */
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writel(0, &pRxMac->mif_ctrl.value);
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/* Initialize the Space Available Register */
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writel(0, &pRxMac->space_avail.value);
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/* Initialize the the mif_ctrl register
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* bit 3: Receive code error. One or more nibbles were signaled as
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* errors during the reception of the packet. Clear this
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* bit in Gigabit, set it in 100Mbit. This was derived
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* experimentally at UNH.
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* bit 4: Receive CRC error. The packet's CRC did not match the
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* internally generated CRC.
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* bit 5: Receive length check error. Indicates that frame length
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* field value in the packet does not match the actual data
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* byte length and is not a type field.
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* bit 16: Receive frame truncated.
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* bit 17: Drop packet enable
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*/
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if (etdev->linkspeed == TRUEPHY_SPEED_100MBPS)
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writel(0x30038, &pRxMac->mif_ctrl.value);
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else
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writel(0x30030, &pRxMac->mif_ctrl.value);
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/* Finally we initialize RxMac to be enabled & WOL disabled. Packet
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* filter is always enabled since it is where the runt packets are
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* supposed to be dropped. For version A silicon, runt packet
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* dropping doesn't work, so it is disabled in the pf_ctrl register,
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* but we still leave the packet filter on.
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*/
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writel(pf_ctrl.value, &pRxMac->pf_ctrl.value);
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writel(0x9, &pRxMac->ctrl.value);
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}
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void ConfigTxMacRegs(struct et131x_adapter *etdev)
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{
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struct _TXMAC_t __iomem *pTxMac = &etdev->regs->txmac;
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TXMAC_CF_PARAM_t Local;
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/* We need to update the Control Frame Parameters
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* cfpt - control frame pause timer set to 64 (0x40)
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* cfep - control frame extended pause timer set to 0x0
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*/
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if (etdev->FlowControl == None) {
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writel(0, &pTxMac->cf_param.value);
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} else {
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Local.bits.cfpt = 0x40;
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Local.bits.cfep = 0x0;
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writel(Local.value, &pTxMac->cf_param.value);
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}
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}
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void ConfigMacStatRegs(struct et131x_adapter *etdev)
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{
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struct _MAC_STAT_t __iomem *pDevMacStat =
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&etdev->regs->macStat;
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/* Next we need to initialize all the MAC_STAT registers to zero on
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* the device.
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*/
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writel(0, &pDevMacStat->RFcs);
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writel(0, &pDevMacStat->RAln);
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writel(0, &pDevMacStat->RFlr);
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writel(0, &pDevMacStat->RDrp);
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writel(0, &pDevMacStat->RCde);
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writel(0, &pDevMacStat->ROvr);
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writel(0, &pDevMacStat->RFrg);
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writel(0, &pDevMacStat->TScl);
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writel(0, &pDevMacStat->TDfr);
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writel(0, &pDevMacStat->TMcl);
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writel(0, &pDevMacStat->TLcl);
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writel(0, &pDevMacStat->TNcl);
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writel(0, &pDevMacStat->TOvr);
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writel(0, &pDevMacStat->TUnd);
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/* Unmask any counters that we want to track the overflow of.
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* Initially this will be all counters. It may become clear later
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* that we do not need to track all counters.
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*/
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{
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MAC_STAT_REG_1_t Carry1M = { 0xffffffff };
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Carry1M.bits.rdrp = 0;
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Carry1M.bits.rjbr = 1;
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Carry1M.bits.rfrg = 0;
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Carry1M.bits.rovr = 0;
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Carry1M.bits.rund = 1;
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Carry1M.bits.rcse = 1;
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Carry1M.bits.rcde = 0;
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Carry1M.bits.rflr = 0;
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Carry1M.bits.raln = 0;
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Carry1M.bits.rxuo = 1;
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Carry1M.bits.rxpf = 1;
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Carry1M.bits.rxcf = 1;
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Carry1M.bits.rbca = 1;
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Carry1M.bits.rmca = 1;
|
|
Carry1M.bits.rfcs = 0;
|
|
Carry1M.bits.rpkt = 1;
|
|
Carry1M.bits.rbyt = 1;
|
|
Carry1M.bits.trmgv = 1;
|
|
Carry1M.bits.trmax = 1;
|
|
Carry1M.bits.tr1k = 1;
|
|
Carry1M.bits.tr511 = 1;
|
|
Carry1M.bits.tr255 = 1;
|
|
Carry1M.bits.tr127 = 1;
|
|
Carry1M.bits.tr64 = 1;
|
|
|
|
writel(Carry1M.value, &pDevMacStat->Carry1M.value);
|
|
}
|
|
|
|
{
|
|
MAC_STAT_REG_2_t Carry2M = { 0xffffffff };
|
|
|
|
Carry2M.bits.tdrp = 1;
|
|
Carry2M.bits.tpfh = 1;
|
|
Carry2M.bits.tncl = 0;
|
|
Carry2M.bits.txcl = 1;
|
|
Carry2M.bits.tlcl = 0;
|
|
Carry2M.bits.tmcl = 0;
|
|
Carry2M.bits.tscl = 0;
|
|
Carry2M.bits.tedf = 1;
|
|
Carry2M.bits.tdfr = 0;
|
|
Carry2M.bits.txpf = 1;
|
|
Carry2M.bits.tbca = 1;
|
|
Carry2M.bits.tmca = 1;
|
|
Carry2M.bits.tpkt = 1;
|
|
Carry2M.bits.tbyt = 1;
|
|
Carry2M.bits.tfrg = 1;
|
|
Carry2M.bits.tund = 0;
|
|
Carry2M.bits.tovr = 0;
|
|
Carry2M.bits.txcf = 1;
|
|
Carry2M.bits.tfcs = 1;
|
|
Carry2M.bits.tjbr = 1;
|
|
|
|
writel(Carry2M.value, &pDevMacStat->Carry2M.value);
|
|
}
|
|
}
|
|
|
|
void ConfigFlowControl(struct et131x_adapter *etdev)
|
|
{
|
|
if (etdev->duplex_mode == 0) {
|
|
etdev->FlowControl = None;
|
|
} else {
|
|
char RemotePause, RemoteAsyncPause;
|
|
|
|
ET1310_PhyAccessMiBit(etdev,
|
|
TRUEPHY_BIT_READ, 5, 10, &RemotePause);
|
|
ET1310_PhyAccessMiBit(etdev,
|
|
TRUEPHY_BIT_READ, 5, 11,
|
|
&RemoteAsyncPause);
|
|
|
|
if ((RemotePause == TRUEPHY_BIT_SET) &&
|
|
(RemoteAsyncPause == TRUEPHY_BIT_SET)) {
|
|
etdev->FlowControl = etdev->RegistryFlowControl;
|
|
} else if ((RemotePause == TRUEPHY_BIT_SET) &&
|
|
(RemoteAsyncPause == TRUEPHY_BIT_CLEAR)) {
|
|
if (etdev->RegistryFlowControl == Both)
|
|
etdev->FlowControl = Both;
|
|
else
|
|
etdev->FlowControl = None;
|
|
} else if ((RemotePause == TRUEPHY_BIT_CLEAR) &&
|
|
(RemoteAsyncPause == TRUEPHY_BIT_CLEAR)) {
|
|
etdev->FlowControl = None;
|
|
} else {/* if (RemotePause == TRUEPHY_CLEAR_BIT &&
|
|
RemoteAsyncPause == TRUEPHY_SET_BIT) */
|
|
if (etdev->RegistryFlowControl == Both)
|
|
etdev->FlowControl = RxOnly;
|
|
else
|
|
etdev->FlowControl = None;
|
|
}
|
|
}
|
|
}
|
|
|
|
/**
|
|
* UpdateMacStatHostCounters - Update the local copy of the statistics
|
|
* @etdev: pointer to the adapter structure
|
|
*/
|
|
void UpdateMacStatHostCounters(struct et131x_adapter *etdev)
|
|
{
|
|
struct _ce_stats_t *stats = &etdev->Stats;
|
|
struct _MAC_STAT_t __iomem *pDevMacStat =
|
|
&etdev->regs->macStat;
|
|
|
|
stats->collisions += readl(&pDevMacStat->TNcl);
|
|
stats->first_collision += readl(&pDevMacStat->TScl);
|
|
stats->tx_deferred += readl(&pDevMacStat->TDfr);
|
|
stats->excessive_collisions += readl(&pDevMacStat->TMcl);
|
|
stats->late_collisions += readl(&pDevMacStat->TLcl);
|
|
stats->tx_uflo += readl(&pDevMacStat->TUnd);
|
|
stats->max_pkt_error += readl(&pDevMacStat->TOvr);
|
|
|
|
stats->alignment_err += readl(&pDevMacStat->RAln);
|
|
stats->crc_err += readl(&pDevMacStat->RCde);
|
|
stats->norcvbuf += readl(&pDevMacStat->RDrp);
|
|
stats->rx_ov_flow += readl(&pDevMacStat->ROvr);
|
|
stats->code_violations += readl(&pDevMacStat->RFcs);
|
|
stats->length_err += readl(&pDevMacStat->RFlr);
|
|
|
|
stats->other_errors += readl(&pDevMacStat->RFrg);
|
|
}
|
|
|
|
/**
|
|
* HandleMacStatInterrupt
|
|
* @etdev: pointer to the adapter structure
|
|
*
|
|
* One of the MACSTAT counters has wrapped. Update the local copy of
|
|
* the statistics held in the adapter structure, checking the "wrap"
|
|
* bit for each counter.
|
|
*/
|
|
void HandleMacStatInterrupt(struct et131x_adapter *etdev)
|
|
{
|
|
MAC_STAT_REG_1_t Carry1;
|
|
MAC_STAT_REG_2_t Carry2;
|
|
|
|
/* Read the interrupt bits from the register(s). These are Clear On
|
|
* Write.
|
|
*/
|
|
Carry1.value = readl(&etdev->regs->macStat.Carry1.value);
|
|
Carry2.value = readl(&etdev->regs->macStat.Carry2.value);
|
|
|
|
writel(Carry1.value, &etdev->regs->macStat.Carry1.value);
|
|
writel(Carry2.value, &etdev->regs->macStat.Carry2.value);
|
|
|
|
/* We need to do update the host copy of all the MAC_STAT counters.
|
|
* For each counter, check it's overflow bit. If the overflow bit is
|
|
* set, then increment the host version of the count by one complete
|
|
* revolution of the counter. This routine is called when the counter
|
|
* block indicates that one of the counters has wrapped.
|
|
*/
|
|
if (Carry1.bits.rfcs)
|
|
etdev->Stats.code_violations += COUNTER_WRAP_16_BIT;
|
|
if (Carry1.bits.raln)
|
|
etdev->Stats.alignment_err += COUNTER_WRAP_12_BIT;
|
|
if (Carry1.bits.rflr)
|
|
etdev->Stats.length_err += COUNTER_WRAP_16_BIT;
|
|
if (Carry1.bits.rfrg)
|
|
etdev->Stats.other_errors += COUNTER_WRAP_16_BIT;
|
|
if (Carry1.bits.rcde)
|
|
etdev->Stats.crc_err += COUNTER_WRAP_16_BIT;
|
|
if (Carry1.bits.rovr)
|
|
etdev->Stats.rx_ov_flow += COUNTER_WRAP_16_BIT;
|
|
if (Carry1.bits.rdrp)
|
|
etdev->Stats.norcvbuf += COUNTER_WRAP_16_BIT;
|
|
if (Carry2.bits.tovr)
|
|
etdev->Stats.max_pkt_error += COUNTER_WRAP_12_BIT;
|
|
if (Carry2.bits.tund)
|
|
etdev->Stats.tx_uflo += COUNTER_WRAP_12_BIT;
|
|
if (Carry2.bits.tscl)
|
|
etdev->Stats.first_collision += COUNTER_WRAP_12_BIT;
|
|
if (Carry2.bits.tdfr)
|
|
etdev->Stats.tx_deferred += COUNTER_WRAP_12_BIT;
|
|
if (Carry2.bits.tmcl)
|
|
etdev->Stats.excessive_collisions += COUNTER_WRAP_12_BIT;
|
|
if (Carry2.bits.tlcl)
|
|
etdev->Stats.late_collisions += COUNTER_WRAP_12_BIT;
|
|
if (Carry2.bits.tncl)
|
|
etdev->Stats.collisions += COUNTER_WRAP_12_BIT;
|
|
}
|
|
|
|
void SetupDeviceForMulticast(struct et131x_adapter *etdev)
|
|
{
|
|
struct _RXMAC_t __iomem *rxmac = &etdev->regs->rxmac;
|
|
uint32_t nIndex;
|
|
uint32_t result;
|
|
uint32_t hash1 = 0;
|
|
uint32_t hash2 = 0;
|
|
uint32_t hash3 = 0;
|
|
uint32_t hash4 = 0;
|
|
u32 pm_csr;
|
|
|
|
/* If ET131X_PACKET_TYPE_MULTICAST is specified, then we provision
|
|
* the multi-cast LIST. If it is NOT specified, (and "ALL" is not
|
|
* specified) then we should pass NO multi-cast addresses to the
|
|
* driver.
|
|
*/
|
|
if (etdev->PacketFilter & ET131X_PACKET_TYPE_MULTICAST) {
|
|
/* Loop through our multicast array and set up the device */
|
|
for (nIndex = 0; nIndex < etdev->MCAddressCount; nIndex++) {
|
|
result = ether_crc(6, etdev->MCList[nIndex]);
|
|
|
|
result = (result & 0x3F800000) >> 23;
|
|
|
|
if (result < 32) {
|
|
hash1 |= (1 << result);
|
|
} else if ((31 < result) && (result < 64)) {
|
|
result -= 32;
|
|
hash2 |= (1 << result);
|
|
} else if ((63 < result) && (result < 96)) {
|
|
result -= 64;
|
|
hash3 |= (1 << result);
|
|
} else {
|
|
result -= 96;
|
|
hash4 |= (1 << result);
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Write out the new hash to the device */
|
|
pm_csr = readl(&etdev->regs->global.pm_csr);
|
|
if ((pm_csr & ET_PM_PHY_SW_COMA) == 0) {
|
|
writel(hash1, &rxmac->multi_hash1);
|
|
writel(hash2, &rxmac->multi_hash2);
|
|
writel(hash3, &rxmac->multi_hash3);
|
|
writel(hash4, &rxmac->multi_hash4);
|
|
}
|
|
}
|
|
|
|
void SetupDeviceForUnicast(struct et131x_adapter *etdev)
|
|
{
|
|
struct _RXMAC_t __iomem *rxmac = &etdev->regs->rxmac;
|
|
RXMAC_UNI_PF_ADDR1_t uni_pf1;
|
|
RXMAC_UNI_PF_ADDR2_t uni_pf2;
|
|
RXMAC_UNI_PF_ADDR3_t uni_pf3;
|
|
u32 pm_csr;
|
|
|
|
/* Set up unicast packet filter reg 3 to be the first two octets of
|
|
* the MAC address for both address
|
|
*
|
|
* Set up unicast packet filter reg 2 to be the octets 2 - 5 of the
|
|
* MAC address for second address
|
|
*
|
|
* Set up unicast packet filter reg 3 to be the octets 2 - 5 of the
|
|
* MAC address for first address
|
|
*/
|
|
uni_pf3.bits.addr1_1 = etdev->CurrentAddress[0];
|
|
uni_pf3.bits.addr1_2 = etdev->CurrentAddress[1];
|
|
uni_pf3.bits.addr2_1 = etdev->CurrentAddress[0];
|
|
uni_pf3.bits.addr2_2 = etdev->CurrentAddress[1];
|
|
|
|
uni_pf2.bits.addr2_3 = etdev->CurrentAddress[2];
|
|
uni_pf2.bits.addr2_4 = etdev->CurrentAddress[3];
|
|
uni_pf2.bits.addr2_5 = etdev->CurrentAddress[4];
|
|
uni_pf2.bits.addr2_6 = etdev->CurrentAddress[5];
|
|
|
|
uni_pf1.bits.addr1_3 = etdev->CurrentAddress[2];
|
|
uni_pf1.bits.addr1_4 = etdev->CurrentAddress[3];
|
|
uni_pf1.bits.addr1_5 = etdev->CurrentAddress[4];
|
|
uni_pf1.bits.addr1_6 = etdev->CurrentAddress[5];
|
|
|
|
pm_csr = readl(&etdev->regs->global.pm_csr);
|
|
if ((pm_csr & ET_PM_PHY_SW_COMA) == 0) {
|
|
writel(uni_pf1.value, &rxmac->uni_pf_addr1.value);
|
|
writel(uni_pf2.value, &rxmac->uni_pf_addr2.value);
|
|
writel(uni_pf3.value, &rxmac->uni_pf_addr3.value);
|
|
}
|
|
}
|