0bc2ecb6e5
Update the device tree to indicate which I2C controller is the DVC controller. AUXDATA needs to be updated too, since the compatible value changed. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
169 lines
3.4 KiB
Plaintext
169 lines
3.4 KiB
Plaintext
/include/ "skeleton.dtsi"
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/ {
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compatible = "nvidia,tegra20";
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interrupt-parent = <&intc>;
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intc: interrupt-controller@50041000 {
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compatible = "arm,cortex-a9-gic";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = < 0x50041000 0x1000 >,
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< 0x50040100 0x0100 >;
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};
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i2c@7000c000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nvidia,tegra20-i2c";
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reg = <0x7000C000 0x100>;
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interrupts = < 0 38 0x04 >;
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};
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i2c@7000c400 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nvidia,tegra20-i2c";
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reg = <0x7000C400 0x100>;
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interrupts = < 0 84 0x04 >;
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};
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i2c@7000c500 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nvidia,tegra20-i2c";
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reg = <0x7000C500 0x100>;
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interrupts = < 0 92 0x04 >;
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};
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i2c@7000d000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nvidia,tegra20-i2c-dvc";
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reg = <0x7000D000 0x200>;
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interrupts = < 0 53 0x04 >;
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};
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i2s@70002800 {
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compatible = "nvidia,tegra20-i2s";
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reg = <0x70002800 0x200>;
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interrupts = < 0 13 0x04 >;
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dma-channel = < 2 >;
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};
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i2s@70002a00 {
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compatible = "nvidia,tegra20-i2s";
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reg = <0x70002a00 0x200>;
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interrupts = < 0 3 0x04 >;
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dma-channel = < 1 >;
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};
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das@70000c00 {
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compatible = "nvidia,tegra20-das";
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reg = <0x70000c00 0x80>;
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};
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gpio: gpio@6000d000 {
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compatible = "nvidia,tegra20-gpio";
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reg = < 0x6000d000 0x1000 >;
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interrupts = < 0 32 0x04
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0 33 0x04
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0 34 0x04
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0 35 0x04
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0 55 0x04
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0 87 0x04
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0 89 0x04 >;
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#gpio-cells = <2>;
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gpio-controller;
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};
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pinmux: pinmux@70000000 {
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compatible = "nvidia,tegra20-pinmux";
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reg = < 0x70000014 0x10 /* Tri-state registers */
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0x70000080 0x20 /* Mux registers */
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0x700000a0 0x14 /* Pull-up/down registers */
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0x70000868 0xa8 >; /* Pad control registers */
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};
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serial@70006000 {
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compatible = "nvidia,tegra20-uart";
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reg = <0x70006000 0x40>;
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reg-shift = <2>;
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interrupts = < 0 36 0x04 >;
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};
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serial@70006040 {
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compatible = "nvidia,tegra20-uart";
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reg = <0x70006040 0x40>;
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reg-shift = <2>;
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interrupts = < 0 37 0x04 >;
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};
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serial@70006200 {
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compatible = "nvidia,tegra20-uart";
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reg = <0x70006200 0x100>;
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reg-shift = <2>;
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interrupts = < 0 46 0x04 >;
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};
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serial@70006300 {
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compatible = "nvidia,tegra20-uart";
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reg = <0x70006300 0x100>;
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reg-shift = <2>;
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interrupts = < 0 90 0x04 >;
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};
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serial@70006400 {
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compatible = "nvidia,tegra20-uart";
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reg = <0x70006400 0x100>;
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reg-shift = <2>;
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interrupts = < 0 91 0x04 >;
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};
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sdhci@c8000000 {
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compatible = "nvidia,tegra20-sdhci";
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reg = <0xc8000000 0x200>;
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interrupts = < 0 14 0x04 >;
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};
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sdhci@c8000200 {
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compatible = "nvidia,tegra20-sdhci";
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reg = <0xc8000200 0x200>;
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interrupts = < 0 15 0x04 >;
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};
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sdhci@c8000400 {
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compatible = "nvidia,tegra20-sdhci";
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reg = <0xc8000400 0x200>;
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interrupts = < 0 19 0x04 >;
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};
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sdhci@c8000600 {
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compatible = "nvidia,tegra20-sdhci";
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reg = <0xc8000600 0x200>;
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interrupts = < 0 31 0x04 >;
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};
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usb@c5000000 {
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compatible = "nvidia,tegra20-ehci", "usb-ehci";
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reg = <0xc5000000 0x4000>;
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interrupts = < 0 20 0x04 >;
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phy_type = "utmi";
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};
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usb@c5004000 {
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compatible = "nvidia,tegra20-ehci", "usb-ehci";
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reg = <0xc5004000 0x4000>;
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interrupts = < 0 21 0x04 >;
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phy_type = "ulpi";
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};
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usb@c5008000 {
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compatible = "nvidia,tegra20-ehci", "usb-ehci";
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reg = <0xc5008000 0x4000>;
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interrupts = < 0 97 0x04 >;
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phy_type = "utmi";
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};
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};
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