bb13b5fdba
Patch from Tony Lindgren This patch by various OMAP developers syncs the OMAP specific arch files with the linux-omap tree. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
570 lines
19 KiB
C
570 lines
19 KiB
C
/*
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* linux/include/asm-arm/arch-omap/mux.h
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*
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* Table of the Omap register configurations for the FUNC_MUX and
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* PULL_DWN combinations.
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*
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* Copyright (C) 2003 Nokia Corporation
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*
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* Written by Tony Lindgren <tony.lindgren@nokia.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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* NOTE: Please use the following naming style for new pin entries.
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* For example, W8_1610_MMC2_DAT0, where:
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* - W8 = ball
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* - 1610 = 1510 or 1610, none if common for both 1510 and 1610
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* - MMC2_DAT0 = function
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*
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* Change log:
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* Added entry for the I2C interface. (02Feb 2004)
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* Copyright (C) 2004 Texas Instruments
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*
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* Added entry for the keypad and uwire CS1. (09Mar 2004)
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* Copyright (C) 2004 Texas Instruments
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*
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*/
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#ifndef __ASM_ARCH_MUX_H
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#define __ASM_ARCH_MUX_H
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#define PU_PD_SEL_NA 0 /* No pu_pd reg available */
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#define PULL_DWN_CTRL_NA 0 /* No pull-down control needed */
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#ifdef CONFIG_OMAP_MUX_DEBUG
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#define MUX_REG(reg, mode_offset, mode) .mux_reg_name = "FUNC_MUX_CTRL_"#reg, \
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.mux_reg = FUNC_MUX_CTRL_##reg, \
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.mask_offset = mode_offset, \
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.mask = mode,
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#define PULL_REG(reg, bit, status) .pull_name = "PULL_DWN_CTRL_"#reg, \
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.pull_reg = PULL_DWN_CTRL_##reg, \
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.pull_bit = bit, \
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.pull_val = status,
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#define PU_PD_REG(reg, status) .pu_pd_name = "PU_PD_SEL_"#reg, \
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.pu_pd_reg = PU_PD_SEL_##reg, \
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.pu_pd_val = status,
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#else
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#define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \
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.mask_offset = mode_offset, \
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.mask = mode,
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#define PULL_REG(reg, bit, status) .pull_reg = PULL_DWN_CTRL_##reg, \
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.pull_bit = bit, \
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.pull_val = status,
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#define PU_PD_REG(reg, status) .pu_pd_reg = PU_PD_SEL_##reg, \
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.pu_pd_val = status,
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#endif /* CONFIG_OMAP_MUX_DEBUG */
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#define MUX_CFG(desc, mux_reg, mode_offset, mode, \
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pull_reg, pull_bit, pull_status, \
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pu_pd_reg, pu_pd_status, debug_status) \
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{ \
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.name = desc, \
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.debug = debug_status, \
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MUX_REG(mux_reg, mode_offset, mode) \
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PULL_REG(pull_reg, pull_bit, pull_status) \
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PU_PD_REG(pu_pd_reg, pu_pd_status) \
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},
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#define PULL_DISABLED 0
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#define PULL_ENABLED 1
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#define PULL_DOWN 0
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#define PULL_UP 1
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typedef struct {
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char *name;
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unsigned char busy;
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unsigned char debug;
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const char *mux_reg_name;
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const unsigned int mux_reg;
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const unsigned char mask_offset;
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const unsigned char mask;
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const char *pull_name;
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const unsigned int pull_reg;
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const unsigned char pull_val;
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const unsigned char pull_bit;
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const char *pu_pd_name;
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const unsigned int pu_pd_reg;
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const unsigned char pu_pd_val;
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} reg_cfg_set;
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/*
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* Lookup table for FUNC_MUX and PULL_DWN register combinations for each
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* device. See also reg_cfg_table below for the register values.
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*/
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typedef enum {
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/* UART1 (BT_UART_GATING)*/
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UART1_TX = 0,
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UART1_RTS,
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/* UART2 (COM_UART_GATING)*/
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UART2_TX,
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UART2_RX,
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UART2_CTS,
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UART2_RTS,
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/* UART3 (GIGA_UART_GATING) */
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UART3_TX,
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UART3_RX,
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UART3_CTS,
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UART3_RTS,
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UART3_CLKREQ,
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UART3_BCLK, /* 12MHz clock out */
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Y15_1610_UART3_RTS,
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/* PWT & PWL */
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PWT,
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PWL,
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/* USB master generic */
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R18_USB_VBUS,
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R18_1510_USB_GPIO0,
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W4_USB_PUEN,
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W4_USB_CLKO,
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W4_USB_HIGHZ,
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W4_GPIO58,
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/* USB1 master */
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USB1_SUSP,
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USB1_SEO,
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W13_1610_USB1_SE0,
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USB1_TXEN,
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USB1_TXD,
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USB1_VP,
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USB1_VM,
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USB1_RCV,
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USB1_SPEED,
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R13_1610_USB1_SPEED,
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R13_1710_USB1_SE0,
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/* USB2 master */
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USB2_SUSP,
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USB2_VP,
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USB2_TXEN,
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USB2_VM,
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USB2_RCV,
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USB2_SEO,
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USB2_TXD,
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/* OMAP-1510 GPIO */
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R18_1510_GPIO0,
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R19_1510_GPIO1,
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M14_1510_GPIO2,
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/* OMAP1610 GPIO */
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P18_1610_GPIO3,
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Y15_1610_GPIO17,
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/* OMAP-1710 GPIO */
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R18_1710_GPIO0,
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V2_1710_GPIO10,
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N21_1710_GPIO14,
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W15_1710_GPIO40,
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/* MPUIO */
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MPUIO2,
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MPUIO4,
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MPUIO5,
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T20_1610_MPUIO5,
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W11_1610_MPUIO6,
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V10_1610_MPUIO7,
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W11_1610_MPUIO9,
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V10_1610_MPUIO10,
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W10_1610_MPUIO11,
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E20_1610_MPUIO13,
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U20_1610_MPUIO14,
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E19_1610_MPUIO15,
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/* MCBSP2 */
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MCBSP2_CLKR,
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MCBSP2_CLKX,
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MCBSP2_DR,
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MCBSP2_DX,
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MCBSP2_FSR,
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MCBSP2_FSX,
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/* MCBSP3 */
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MCBSP3_CLKX,
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/* Misc ballouts */
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BALLOUT_V8_ARMIO3,
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/* OMAP-1610 MMC2 */
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W8_1610_MMC2_DAT0,
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V8_1610_MMC2_DAT1,
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W15_1610_MMC2_DAT2,
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R10_1610_MMC2_DAT3,
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Y10_1610_MMC2_CLK,
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Y8_1610_MMC2_CMD,
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V9_1610_MMC2_CMDDIR,
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V5_1610_MMC2_DATDIR0,
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W19_1610_MMC2_DATDIR1,
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R18_1610_MMC2_CLKIN,
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/* OMAP-1610 External Trace Interface */
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M19_1610_ETM_PSTAT0,
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L15_1610_ETM_PSTAT1,
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L18_1610_ETM_PSTAT2,
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L19_1610_ETM_D0,
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J19_1610_ETM_D6,
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J18_1610_ETM_D7,
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/* OMAP16XX GPIO */
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P20_1610_GPIO4,
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V9_1610_GPIO7,
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W8_1610_GPIO9,
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N19_1610_GPIO13,
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P10_1610_GPIO22,
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V5_1610_GPIO24,
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AA20_1610_GPIO_41,
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W19_1610_GPIO48,
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M7_1610_GPIO62,
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V14_16XX_GPIO37,
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R9_16XX_GPIO18,
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L14_16XX_GPIO49,
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/* OMAP-1610 uWire */
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V19_1610_UWIRE_SCLK,
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U18_1610_UWIRE_SDI,
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W21_1610_UWIRE_SDO,
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N14_1610_UWIRE_CS0,
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P15_1610_UWIRE_CS0,
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N15_1610_UWIRE_CS1,
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/* OMAP-1610 Flash */
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L3_1610_FLASH_CS2B_OE,
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M8_1610_FLASH_CS2B_WE,
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/* First MMC */
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MMC_CMD,
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MMC_DAT1,
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MMC_DAT2,
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MMC_DAT0,
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MMC_CLK,
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MMC_DAT3,
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/* OMAP-1710 MMC CMDDIR and DATDIR0 */
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M15_1710_MMC_CLKI,
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P19_1710_MMC_CMDDIR,
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P20_1710_MMC_DATDIR0,
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/* OMAP-1610 USB0 alternate pin configuration */
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W9_USB0_TXEN,
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AA9_USB0_VP,
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Y5_USB0_RCV,
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R9_USB0_VM,
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V6_USB0_TXD,
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W5_USB0_SE0,
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V9_USB0_SPEED,
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V9_USB0_SUSP,
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/* USB2 */
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W9_USB2_TXEN,
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AA9_USB2_VP,
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Y5_USB2_RCV,
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R9_USB2_VM,
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V6_USB2_TXD,
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W5_USB2_SE0,
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/* 16XX UART */
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R13_1610_UART1_TX,
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V14_16XX_UART1_RX,
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R14_1610_UART1_CTS,
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AA15_1610_UART1_RTS,
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R9_16XX_UART2_RX,
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L14_16XX_UART3_RX,
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/* I2C OMAP-1610 */
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I2C_SCL,
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I2C_SDA,
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/* Keypad */
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F18_1610_KBC0,
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D20_1610_KBC1,
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D19_1610_KBC2,
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E18_1610_KBC3,
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C21_1610_KBC4,
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G18_1610_KBR0,
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F19_1610_KBR1,
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H14_1610_KBR2,
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E20_1610_KBR3,
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E19_1610_KBR4,
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N19_1610_KBR5,
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/* Power management */
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T20_1610_LOW_PWR,
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/* MCLK Settings */
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V5_1710_MCLK_ON,
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V5_1710_MCLK_OFF,
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R10_1610_MCLK_ON,
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R10_1610_MCLK_OFF,
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/* CompactFlash controller */
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P11_1610_CF_CD2,
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R11_1610_CF_IOIS16,
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V10_1610_CF_IREQ,
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W10_1610_CF_RESET,
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W11_1610_CF_CD1,
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} reg_cfg_t;
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#if defined(__MUX_C__) && defined(CONFIG_OMAP_MUX)
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/*
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* Table of various FUNC_MUX and PULL_DWN combinations for each device.
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* See also reg_cfg_t above for the lookup table.
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*/
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static const reg_cfg_set __initdata_or_module
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reg_cfg_table[] = {
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/*
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* description mux mode mux pull pull pull pu_pd pu dbg
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* reg offset mode reg bit ena reg
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*/
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MUX_CFG("UART1_TX", 9, 21, 1, 2, 3, 0, NA, 0, 0)
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MUX_CFG("UART1_RTS", 9, 12, 1, 2, 0, 0, NA, 0, 0)
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/* UART2 (COM_UART_GATING), conflicts with USB2 */
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MUX_CFG("UART2_TX", C, 27, 1, 3, 3, 0, NA, 0, 0)
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MUX_CFG("UART2_RX", C, 18, 0, 3, 1, 1, NA, 0, 0)
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MUX_CFG("UART2_CTS", C, 21, 0, 3, 1, 1, NA, 0, 0)
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MUX_CFG("UART2_RTS", C, 24, 1, 3, 2, 0, NA, 0, 0)
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/* UART3 (GIGA_UART_GATING) */
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MUX_CFG("UART3_TX", 6, 0, 1, 0, 30, 0, NA, 0, 0)
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MUX_CFG("UART3_RX", 6, 3, 0, 0, 31, 1, NA, 0, 0)
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MUX_CFG("UART3_CTS", 5, 12, 2, 0, 24, 0, NA, 0, 0)
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MUX_CFG("UART3_RTS", 5, 15, 2, 0, 25, 0, NA, 0, 0)
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MUX_CFG("UART3_CLKREQ", 9, 27, 0, 2, 5, 0, NA, 0, 0)
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MUX_CFG("UART3_BCLK", A, 0, 0, 2, 6, 0, NA, 0, 0)
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MUX_CFG("Y15_1610_UART3_RTS", A, 0, 1, 2, 6, 0, NA, 0, 0)
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/* PWT & PWL, conflicts with UART3 */
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MUX_CFG("PWT", 6, 0, 2, 0, 30, 0, NA, 0, 0)
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MUX_CFG("PWL", 6, 3, 1, 0, 31, 1, NA, 0, 0)
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/* USB internal master generic */
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MUX_CFG("R18_USB_VBUS", 7, 9, 2, 1, 11, 0, NA, 0, 1)
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MUX_CFG("R18_1510_USB_GPIO0", 7, 9, 0, 1, 11, 1, NA, 0, 1)
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/* works around erratum: W4_USB_PUEN and W4_USB_PUDIS are switched! */
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MUX_CFG("W4_USB_PUEN", D, 3, 3, 3, 5, 1, NA, 0, 1)
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MUX_CFG("W4_USB_CLKO", D, 3, 1, 3, 5, 0, NA, 0, 1)
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MUX_CFG("W4_USB_HIGHZ", D, 3, 4, 3, 5, 0, 3, 0, 1)
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MUX_CFG("W4_GPIO58", D, 3, 7, 3, 5, 0, 3, 0, 1)
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/* USB1 master */
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MUX_CFG("USB1_SUSP", 8, 27, 2, 1, 27, 0, NA, 0, 1)
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MUX_CFG("USB1_SE0", 9, 0, 2, 1, 28, 0, NA, 0, 1)
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MUX_CFG("W13_1610_USB1_SE0", 9, 0, 4, 1, 28, 0, NA, 0, 1)
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MUX_CFG("USB1_TXEN", 9, 3, 2, 1, 29, 0, NA, 0, 1)
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MUX_CFG("USB1_TXD", 9, 24, 1, 2, 4, 0, NA, 0, 1)
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MUX_CFG("USB1_VP", A, 3, 1, 2, 7, 0, NA, 0, 1)
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MUX_CFG("USB1_VM", A, 6, 1, 2, 8, 0, NA, 0, 1)
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MUX_CFG("USB1_RCV", A, 9, 1, 2, 9, 0, NA, 0, 1)
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MUX_CFG("USB1_SPEED", A, 12, 2, 2, 10, 0, NA, 0, 1)
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MUX_CFG("R13_1610_USB1_SPEED", A, 12, 5, 2, 10, 0, NA, 0, 1)
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MUX_CFG("R13_1710_USB1_SEO", A, 12, 5, 2, 10, 0, NA, 0, 1)
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/* USB2 master */
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MUX_CFG("USB2_SUSP", B, 3, 1, 2, 17, 0, NA, 0, 1)
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MUX_CFG("USB2_VP", B, 6, 1, 2, 18, 0, NA, 0, 1)
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MUX_CFG("USB2_TXEN", B, 9, 1, 2, 19, 0, NA, 0, 1)
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MUX_CFG("USB2_VM", C, 18, 1, 3, 0, 0, NA, 0, 1)
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MUX_CFG("USB2_RCV", C, 21, 1, 3, 1, 0, NA, 0, 1)
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MUX_CFG("USB2_SE0", C, 24, 2, 3, 2, 0, NA, 0, 1)
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MUX_CFG("USB2_TXD", C, 27, 2, 3, 3, 0, NA, 0, 1)
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/* OMAP-1510 GPIO */
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MUX_CFG("R18_1510_GPIO0", 7, 9, 0, 1, 11, 1, 0, 0, 1)
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MUX_CFG("R19_1510_GPIO1", 7, 6, 0, 1, 10, 1, 0, 0, 1)
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MUX_CFG("M14_1510_GPIO2", 7, 3, 0, 1, 9, 1, 0, 0, 1)
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/* OMAP1610 GPIO */
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MUX_CFG("P18_1610_GPIO3", 7, 0, 0, 1, 8, 0, NA, 0, 1)
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MUX_CFG("Y15_1610_GPIO17", A, 0, 7, 2, 6, 0, NA, 0, 1)
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/* OMAP-1710 GPIO */
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MUX_CFG("R18_1710_GPIO0", 7, 9, 0, 1, 11, 1, 1, 1, 1)
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MUX_CFG("V2_1710_GPIO10", F, 27, 1, 4, 3, 1, 4, 1, 1)
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MUX_CFG("N21_1710_GPIO14", 6, 9, 0, 1, 1, 1, 1, 1, 1)
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MUX_CFG("W15_1710_GPIO40", 9, 27, 7, 2, 5, 1, 2, 1, 1)
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/* MPUIO */
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MUX_CFG("MPUIO2", 7, 18, 0, 1, 1, 1, NA, 0, 1)
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MUX_CFG("MPUIO4", 7, 15, 0, 1, 13, 1, NA, 0, 1)
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MUX_CFG("MPUIO5", 7, 12, 0, 1, 12, 1, NA, 0, 1)
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MUX_CFG("T20_1610_MPUIO5", 7, 12, 0, 1, 12, 0, 3, 0, 1)
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MUX_CFG("W11_1610_MPUIO6", 10, 15, 2, 3, 8, 0, 3, 0, 1)
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MUX_CFG("V10_1610_MPUIO7", A, 24, 2, 2, 14, 0, 2, 0, 1)
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MUX_CFG("W11_1610_MPUIO9", 10, 15, 1, 3, 8, 0, 3, 0, 1)
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MUX_CFG("V10_1610_MPUIO10", A, 24, 1, 2, 14, 0, 2, 0, 1)
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MUX_CFG("W10_1610_MPUIO11", A, 18, 2, 2, 11, 0, 2, 0, 1)
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MUX_CFG("E20_1610_MPUIO13", 3, 21, 1, 0, 7, 0, 0, 0, 1)
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MUX_CFG("U20_1610_MPUIO14", 9, 6, 6, 0, 30, 0, 0, 0, 1)
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MUX_CFG("E19_1610_MPUIO15", 3, 18, 1, 0, 6, 0, 0, 0, 1)
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/* MCBSP2 */
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MUX_CFG("MCBSP2_CLKR", C, 6, 0, 2, 27, 1, NA, 0, 1)
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MUX_CFG("MCBSP2_CLKX", C, 9, 0, 2, 29, 1, NA, 0, 1)
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MUX_CFG("MCBSP2_DR", C, 0, 0, 2, 26, 1, NA, 0, 1)
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MUX_CFG("MCBSP2_DX", C, 15, 0, 2, 31, 1, NA, 0, 1)
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MUX_CFG("MCBSP2_FSR", C, 12, 0, 2, 30, 1, NA, 0, 1)
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MUX_CFG("MCBSP2_FSX", C, 3, 0, 2, 27, 1, NA, 0, 1)
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|
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/* MCBSP3 NOTE: Mode must 1 for clock */
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MUX_CFG("MCBSP3_CLKX", 9, 3, 1, 1, 29, 0, NA, 0, 1)
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|
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/* Misc ballouts */
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MUX_CFG("BALLOUT_V8_ARMIO3", B, 18, 0, 2, 25, 1, NA, 0, 1)
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|
|
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/* OMAP-1610 MMC2 */
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MUX_CFG("W8_1610_MMC2_DAT0", B, 21, 6, 2, 23, 1, 2, 1, 1)
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MUX_CFG("V8_1610_MMC2_DAT1", B, 27, 6, 2, 25, 1, 2, 1, 1)
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MUX_CFG("W15_1610_MMC2_DAT2", 9, 12, 6, 2, 5, 1, 2, 1, 1)
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MUX_CFG("R10_1610_MMC2_DAT3", B, 18, 6, 2, 22, 1, 2, 1, 1)
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MUX_CFG("Y10_1610_MMC2_CLK", B, 3, 6, 2, 17, 0, 2, 0, 1)
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MUX_CFG("Y8_1610_MMC2_CMD", B, 24, 6, 2, 24, 1, 2, 1, 1)
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MUX_CFG("V9_1610_MMC2_CMDDIR", B, 12, 6, 2, 20, 0, 2, 1, 1)
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MUX_CFG("V5_1610_MMC2_DATDIR0", B, 15, 6, 2, 21, 0, 2, 1, 1)
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MUX_CFG("W19_1610_MMC2_DATDIR1", 8, 15, 6, 1, 23, 0, 1, 1, 1)
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MUX_CFG("R18_1610_MMC2_CLKIN", 7, 9, 6, 1, 11, 0, 1, 11, 1)
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|
|
|
/* OMAP-1610 External Trace Interface */
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MUX_CFG("M19_1610_ETM_PSTAT0", 5, 27, 1, 0, 29, 0, 0, 0, 1)
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MUX_CFG("L15_1610_ETM_PSTAT1", 5, 24, 1, 0, 28, 0, 0, 0, 1)
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MUX_CFG("L18_1610_ETM_PSTAT2", 5, 21, 1, 0, 27, 0, 0, 0, 1)
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MUX_CFG("L19_1610_ETM_D0", 5, 18, 1, 0, 26, 0, 0, 0, 1)
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|
MUX_CFG("J19_1610_ETM_D6", 5, 0, 1, 0, 20, 0, 0, 0, 1)
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MUX_CFG("J18_1610_ETM_D7", 5, 27, 1, 0, 19, 0, 0, 0, 1)
|
|
|
|
/* OMAP16XX GPIO */
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MUX_CFG("P20_1610_GPIO4", 6, 27, 0, 1, 7, 0, 1, 1, 1)
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MUX_CFG("V9_1610_GPIO7", B, 12, 1, 2, 20, 0, 2, 1, 1)
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MUX_CFG("W8_1610_GPIO9", B, 21, 0, 2, 23, 0, 2, 1, 1)
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MUX_CFG("N19_1610_GPIO13", 6, 12, 0, 1, 2, 0, 1, 1, 1)
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|
MUX_CFG("P10_1610_GPIO22", C, 0, 7, 2, 26, 0, 2, 1, 1)
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|
MUX_CFG("V5_1610_GPIO24", B, 15, 7, 2, 21, 0, 2, 1, 1)
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|
MUX_CFG("AA20_1610_GPIO_41", 9, 9, 7, 1, 31, 0, 1, 1, 1)
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|
MUX_CFG("W19_1610_GPIO48", 8, 15, 7, 1, 23, 1, 1, 0, 1)
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|
MUX_CFG("M7_1610_GPIO62", 10, 0, 0, 4, 24, 0, 4, 0, 1)
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|
MUX_CFG("V14_16XX_GPIO37", 9, 18, 7, 2, 2, 0, 2, 2, 0)
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|
MUX_CFG("R9_16XX_GPIO18", C, 18, 7, 3, 0, 0, 3, 0, 0)
|
|
MUX_CFG("L14_16XX_GPIO49", 6, 3, 7, 0, 31, 0, 0, 31, 0)
|
|
|
|
/* OMAP-1610 uWire */
|
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MUX_CFG("V19_1610_UWIRE_SCLK", 8, 6, 0, 1, 20, 0, 1, 1, 1)
|
|
MUX_CFG("U18_1610_UWIRE_SDI", 8, 0, 0, 1, 18, 0, 1, 1, 1)
|
|
MUX_CFG("W21_1610_UWIRE_SDO", 8, 3, 0, 1, 19, 0, 1, 1, 1)
|
|
MUX_CFG("N14_1610_UWIRE_CS0", 8, 9, 1, 1, 21, 0, 1, 1, 1)
|
|
MUX_CFG("P15_1610_UWIRE_CS3", 8, 12, 1, 1, 22, 0, 1, 1, 1)
|
|
MUX_CFG("N15_1610_UWIRE_CS1", 7, 18, 2, 1, 14, 0, NA, 0, 1)
|
|
|
|
/* OMAP-1610 Flash */
|
|
MUX_CFG("L3_1610_FLASH_CS2B_OE",10, 6, 1, NA, 0, 0, NA, 0, 1)
|
|
MUX_CFG("M8_1610_FLASH_CS2B_WE",10, 3, 1, NA, 0, 0, NA, 0, 1)
|
|
|
|
/* First MMC interface, same on 1510, 1610 and 1710 */
|
|
MUX_CFG("MMC_CMD", A, 27, 0, 2, 15, 1, 2, 1, 1)
|
|
MUX_CFG("MMC_DAT1", A, 24, 0, 2, 14, 1, 2, 1, 1)
|
|
MUX_CFG("MMC_DAT2", A, 18, 0, 2, 12, 1, 2, 1, 1)
|
|
MUX_CFG("MMC_DAT0", B, 0, 0, 2, 16, 1, 2, 1, 1)
|
|
MUX_CFG("MMC_CLK", A, 21, 0, NA, 0, 0, NA, 0, 1)
|
|
MUX_CFG("MMC_DAT3", 10, 15, 0, 3, 8, 1, 3, 1, 1)
|
|
MUX_CFG("M15_1710_MMC_CLKI", 6, 21, 2, 0, 0, 0, NA, 0, 1)
|
|
MUX_CFG("P19_1710_MMC_CMDDIR", 6, 24, 6, 0, 0, 0, NA, 0, 1)
|
|
MUX_CFG("P20_1710_MMC_DATDIR0", 6, 27, 5, 0, 0, 0, NA, 0, 1)
|
|
|
|
/* OMAP-1610 USB0 alternate configuration */
|
|
MUX_CFG("W9_USB0_TXEN", B, 9, 5, 2, 19, 0, 2, 0, 1)
|
|
MUX_CFG("AA9_USB0_VP", B, 6, 5, 2, 18, 0, 2, 0, 1)
|
|
MUX_CFG("Y5_USB0_RCV", C, 21, 5, 3, 1, 0, 1, 0, 1)
|
|
MUX_CFG("R9_USB0_VM", C, 18, 5, 3, 0, 0, 3, 0, 1)
|
|
MUX_CFG("V6_USB0_TXD", C, 27, 5, 3, 3, 0, 3, 0, 1)
|
|
MUX_CFG("W5_USB0_SE0", C, 24, 5, 3, 2, 0, 3, 0, 1)
|
|
MUX_CFG("V9_USB0_SPEED", B, 12, 5, 2, 20, 0, 2, 0, 1)
|
|
MUX_CFG("Y10_USB0_SUSP", B, 3, 5, 2, 17, 0, 2, 0, 1)
|
|
|
|
/* USB2 interface */
|
|
MUX_CFG("W9_USB2_TXEN", B, 9, 1, NA, 0, 0, NA, 0, 1)
|
|
MUX_CFG("AA9_USB2_VP", B, 6, 1, NA, 0, 0, NA, 0, 1)
|
|
MUX_CFG("Y5_USB2_RCV", C, 21, 1, NA, 0, 0, NA, 0, 1)
|
|
MUX_CFG("R9_USB2_VM", C, 18, 1, NA, 0, 0, NA, 0, 1)
|
|
MUX_CFG("V6_USB2_TXD", C, 27, 2, NA, 0, 0, NA, 0, 1)
|
|
MUX_CFG("W5_USB2_SE0", C, 24, 2, NA, 0, 0, NA, 0, 1)
|
|
|
|
/* 16XX UART */
|
|
MUX_CFG("R13_1610_UART1_TX", A, 12, 6, 2, 10, 0, 2, 10, 1)
|
|
MUX_CFG("V14_16XX_UART1_RX", 9, 18, 0, 2, 2, 0, 2, 2, 1)
|
|
MUX_CFG("R14_1610_UART1_CTS", 9, 15, 0, 2, 1, 0, 2, 1, 1)
|
|
MUX_CFG("AA15_1610_UART1_RTS", 9, 12, 1, 2, 0, 0, 2, 0, 1)
|
|
MUX_CFG("R9_16XX_UART2_RX", C, 18, 0, 3, 0, 0, 3, 0, 1)
|
|
MUX_CFG("L14_16XX_UART3_RX", 6, 3, 0, 0, 31, 0, 0, 31, 1)
|
|
|
|
/* I2C interface */
|
|
MUX_CFG("I2C_SCL", 7, 24, 0, NA, 0, 0, NA, 0, 0)
|
|
MUX_CFG("I2C_SDA", 7, 27, 0, NA, 0, 0, NA, 0, 0)
|
|
|
|
/* Keypad */
|
|
MUX_CFG("F18_1610_KBC0", 3, 15, 0, 0, 5, 1, 0, 0, 0)
|
|
MUX_CFG("D20_1610_KBC1", 3, 12, 0, 0, 4, 1, 0, 0, 0)
|
|
MUX_CFG("D19_1610_KBC2", 3, 9, 0, 0, 3, 1, 0, 0, 0)
|
|
MUX_CFG("E18_1610_KBC3", 3, 6, 0, 0, 2, 1, 0, 0, 0)
|
|
MUX_CFG("C21_1610_KBC4", 3, 3, 0, 0, 1, 1, 0, 0, 0)
|
|
MUX_CFG("G18_1610_KBR0", 4, 0, 0, 0, 10, 1, 0, 1, 0)
|
|
MUX_CFG("F19_1610_KBR1", 3, 27, 0, 0, 9, 1, 0, 1, 0)
|
|
MUX_CFG("H14_1610_KBR2", 3, 24, 0, 0, 8, 1, 0, 1, 0)
|
|
MUX_CFG("E20_1610_KBR3", 3, 21, 0, 0, 7, 1, 0, 1, 0)
|
|
MUX_CFG("E19_1610_KBR4", 3, 18, 0, 0, 6, 1, 0, 1, 0)
|
|
MUX_CFG("N19_1610_KBR5", 6, 12, 1, 1, 2, 1, 1, 1, 0)
|
|
|
|
/* Power management */
|
|
MUX_CFG("T20_1610_LOW_PWR", 7, 12, 1, NA, 0, 0, NA, 0, 0)
|
|
|
|
/* MCLK Settings */
|
|
MUX_CFG("V5_1710_MCLK_ON", B, 15, 0, NA, 0, 0, NA, 0, 0)
|
|
MUX_CFG("V5_1710_MCLK_OFF", B, 15, 6, NA, 0, 0, NA, 0, 0)
|
|
MUX_CFG("R10_1610_MCLK_ON", B, 18, 0, NA, 22, 0, NA, 1, 0)
|
|
MUX_CFG("R10_1610_MCLK_OFF", B, 18, 6, 2, 22, 1, 2, 1, 1)
|
|
|
|
/* CompactFlash controller, conflicts with MMC1 */
|
|
MUX_CFG("P11_1610_CF_CD2", A, 27, 3, 2, 15, 1, 2, 1, 1)
|
|
MUX_CFG("R11_1610_CF_IOIS16", B, 0, 3, 2, 16, 1, 2, 1, 1)
|
|
MUX_CFG("V10_1610_CF_IREQ", A, 24, 3, 2, 14, 0, 2, 0, 1)
|
|
MUX_CFG("W10_1610_CF_RESET", A, 18, 3, 2, 12, 1, 2, 1, 1)
|
|
MUX_CFG("W11_1610_CF_CD1", 10, 15, 3, 3, 8, 1, 3, 1, 1)
|
|
};
|
|
|
|
#endif /* __MUX_C__ */
|
|
|
|
#ifdef CONFIG_OMAP_MUX
|
|
/* setup pin muxing in Linux */
|
|
extern int omap_cfg_reg(reg_cfg_t reg_cfg);
|
|
#else
|
|
/* boot loader does it all (no warnings from CONFIG_OMAP_MUX_WARNINGS) */
|
|
static inline int omap_cfg_reg(reg_cfg_t reg_cfg) { return 0; }
|
|
#endif
|
|
|
|
#endif
|