72da0b07b1
As with any other such change, the goal is to prevent inadvertent writes to these structures (assuming DEBUG_RODATA is enabled), and to separate data (possibly frequently) written to from such never getting modified. Reviewed-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Jan Beulich <jbeulich@novell.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
316 lines
9.4 KiB
C
316 lines
9.4 KiB
C
/*
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* Low-level PCI config space access for OLPC systems who lack the VSA
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* PCI virtualization software.
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*
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* Copyright © 2006 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* The AMD Geode chipset (ie: GX2 processor, cs5536 I/O companion device)
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* has some I/O functions (display, southbridge, sound, USB HCIs, etc)
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* that more or less behave like PCI devices, but the hardware doesn't
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* directly implement the PCI configuration space headers. AMD provides
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* "VSA" (Virtual System Architecture) software that emulates PCI config
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* space for these devices, by trapping I/O accesses to PCI config register
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* (CF8/CFC) and running some code in System Management Mode interrupt state.
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* On the OLPC platform, we don't want to use that VSA code because
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* (a) it slows down suspend/resume, and (b) recompiling it requires special
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* compilers that are hard to get. So instead of letting the complex VSA
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* code simulate the PCI config registers for the on-chip devices, we
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* just simulate them the easy way, by inserting the code into the
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* pci_write_config and pci_read_config path. Most of the config registers
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* are read-only anyway, so the bulk of the simulation is just table lookup.
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*/
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <asm/olpc.h>
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#include <asm/geode.h>
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#include <asm/pci_x86.h>
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/*
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* In the tables below, the first two line (8 longwords) are the
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* size masks that are used when the higher level PCI code determines
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* the size of the region by writing ~0 to a base address register
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* and reading back the result.
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*
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* The following lines are the values that are read during normal
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* PCI config access cycles, i.e. not after just having written
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* ~0 to a base address register.
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*/
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static const uint32_t lxnb_hdr[] = { /* dev 1 function 0 - devfn = 8 */
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0x0, 0x0, 0x0, 0x0,
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0x0, 0x0, 0x0, 0x0,
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0x281022, 0x2200005, 0x6000021, 0x80f808, /* AMD Vendor ID */
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0x0, 0x0, 0x0, 0x0, /* No virtual registers, hence no BAR */
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0x0, 0x0, 0x0, 0x28100b,
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0x0, 0x0, 0x0, 0x0,
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0x0, 0x0, 0x0, 0x0,
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0x0, 0x0, 0x0, 0x0,
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0x0, 0x0, 0x0, 0x0,
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};
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static const uint32_t gxnb_hdr[] = { /* dev 1 function 0 - devfn = 8 */
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0xfffffffd, 0x0, 0x0, 0x0,
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0x0, 0x0, 0x0, 0x0,
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0x28100b, 0x2200005, 0x6000021, 0x80f808, /* NSC Vendor ID */
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0xac1d, 0x0, 0x0, 0x0, /* I/O BAR - base of virtual registers */
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0x0, 0x0, 0x0, 0x28100b,
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0x0, 0x0, 0x0, 0x0,
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0x0, 0x0, 0x0, 0x0,
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0x0, 0x0, 0x0, 0x0,
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0x0, 0x0, 0x0, 0x0,
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};
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static const uint32_t lxfb_hdr[] = { /* dev 1 function 1 - devfn = 9 */
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0xff000008, 0xffffc000, 0xffffc000, 0xffffc000,
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0xffffc000, 0x0, 0x0, 0x0,
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0x20811022, 0x2200003, 0x3000000, 0x0, /* AMD Vendor ID */
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0xfd000000, 0xfe000000, 0xfe004000, 0xfe008000, /* FB, GP, VG, DF */
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0xfe00c000, 0x0, 0x0, 0x30100b, /* VIP */
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0x0, 0x0, 0x0, 0x10e, /* INTA, IRQ14 for graphics accel */
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0x0, 0x0, 0x0, 0x0,
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0x3d0, 0x3c0, 0xa0000, 0x0, /* VG IO, VG IO, EGA FB, MONO FB */
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0x0, 0x0, 0x0, 0x0,
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};
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static const uint32_t gxfb_hdr[] = { /* dev 1 function 1 - devfn = 9 */
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0xff800008, 0xffffc000, 0xffffc000, 0xffffc000,
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0x0, 0x0, 0x0, 0x0,
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0x30100b, 0x2200003, 0x3000000, 0x0, /* NSC Vendor ID */
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0xfd000000, 0xfe000000, 0xfe004000, 0xfe008000, /* FB, GP, VG, DF */
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0x0, 0x0, 0x0, 0x30100b,
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0x0, 0x0, 0x0, 0x0,
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0x0, 0x0, 0x0, 0x0,
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0x3d0, 0x3c0, 0xa0000, 0x0, /* VG IO, VG IO, EGA FB, MONO FB */
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0x0, 0x0, 0x0, 0x0,
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};
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static const uint32_t aes_hdr[] = { /* dev 1 function 2 - devfn = 0xa */
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0xffffc000, 0x0, 0x0, 0x0,
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0x0, 0x0, 0x0, 0x0,
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0x20821022, 0x2a00006, 0x10100000, 0x8, /* NSC Vendor ID */
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0xfe010000, 0x0, 0x0, 0x0, /* AES registers */
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0x0, 0x0, 0x0, 0x20821022,
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0x0, 0x0, 0x0, 0x0,
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0x0, 0x0, 0x0, 0x0,
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0x0, 0x0, 0x0, 0x0,
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0x0, 0x0, 0x0, 0x0,
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};
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static const uint32_t isa_hdr[] = { /* dev f function 0 - devfn = 78 */
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0xfffffff9, 0xffffff01, 0xffffffc1, 0xffffffe1,
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0xffffff81, 0xffffffc1, 0x0, 0x0,
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0x20901022, 0x2a00049, 0x6010003, 0x802000,
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0x18b1, 0x1001, 0x1801, 0x1881, /* SMB-8 GPIO-256 MFGPT-64 IRQ-32 */
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0x1401, 0x1841, 0x0, 0x20901022, /* PMS-128 ACPI-64 */
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0x0, 0x0, 0x0, 0x0,
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0x0, 0x0, 0x0, 0x0,
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0x0, 0x0, 0x0, 0xaa5b, /* IRQ steering */
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0x0, 0x0, 0x0, 0x0,
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};
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static const uint32_t ac97_hdr[] = { /* dev f function 3 - devfn = 7b */
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0xffffff81, 0x0, 0x0, 0x0,
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0x0, 0x0, 0x0, 0x0,
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0x20931022, 0x2a00041, 0x4010001, 0x0,
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0x1481, 0x0, 0x0, 0x0, /* I/O BAR-128 */
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0x0, 0x0, 0x0, 0x20931022,
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0x0, 0x0, 0x0, 0x205, /* IntB, IRQ5 */
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0x0, 0x0, 0x0, 0x0,
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0x0, 0x0, 0x0, 0x0,
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0x0, 0x0, 0x0, 0x0,
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};
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static const uint32_t ohci_hdr[] = { /* dev f function 4 - devfn = 7c */
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0xfffff000, 0x0, 0x0, 0x0,
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0x0, 0x0, 0x0, 0x0,
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0x20941022, 0x2300006, 0xc031002, 0x0,
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0xfe01a000, 0x0, 0x0, 0x0, /* MEMBAR-1000 */
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0x0, 0x0, 0x0, 0x20941022,
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0x0, 0x40, 0x0, 0x40a, /* CapPtr INT-D, IRQA */
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0xc8020001, 0x0, 0x0, 0x0, /* Capabilities - 40 is R/O,
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44 is mask 8103 (power control) */
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0x0, 0x0, 0x0, 0x0,
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0x0, 0x0, 0x0, 0x0,
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};
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static const uint32_t ehci_hdr[] = { /* dev f function 4 - devfn = 7d */
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0xfffff000, 0x0, 0x0, 0x0,
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0x0, 0x0, 0x0, 0x0,
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0x20951022, 0x2300006, 0xc032002, 0x0,
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0xfe01b000, 0x0, 0x0, 0x0, /* MEMBAR-1000 */
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0x0, 0x0, 0x0, 0x20951022,
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0x0, 0x40, 0x0, 0x40a, /* CapPtr INT-D, IRQA */
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0xc8020001, 0x0, 0x0, 0x0, /* Capabilities - 40 is R/O, 44 is
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mask 8103 (power control) */
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#if 0
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0x1, 0x40080000, 0x0, 0x0, /* EECP - see EHCI spec section 2.1.7 */
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#endif
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0x01000001, 0x0, 0x0, 0x0, /* EECP - see EHCI spec section 2.1.7 */
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0x2020, 0x0, 0x0, 0x0, /* (EHCI page 8) 60 SBRN (R/O),
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61 FLADJ (R/W), PORTWAKECAP */
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};
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static uint32_t ff_loc = ~0;
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static uint32_t zero_loc;
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static int bar_probing; /* Set after a write of ~0 to a BAR */
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static int is_lx;
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#define NB_SLOT 0x1 /* Northbridge - GX chip - Device 1 */
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#define SB_SLOT 0xf /* Southbridge - CS5536 chip - Device F */
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static int is_simulated(unsigned int bus, unsigned int devfn)
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{
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return (!bus && ((PCI_SLOT(devfn) == NB_SLOT) ||
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(PCI_SLOT(devfn) == SB_SLOT)));
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}
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static uint32_t *hdr_addr(const uint32_t *hdr, int reg)
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{
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uint32_t addr;
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/*
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* This is a little bit tricky. The header maps consist of
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* 0x20 bytes of size masks, followed by 0x70 bytes of header data.
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* In the normal case, when not probing a BAR's size, we want
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* to access the header data, so we add 0x20 to the reg offset,
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* thus skipping the size mask area.
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* In the BAR probing case, we want to access the size mask for
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* the BAR, so we subtract 0x10 (the config header offset for
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* BAR0), and don't skip the size mask area.
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*/
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addr = (uint32_t)hdr + reg + (bar_probing ? -0x10 : 0x20);
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bar_probing = 0;
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return (uint32_t *)addr;
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}
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static int pci_olpc_read(unsigned int seg, unsigned int bus,
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unsigned int devfn, int reg, int len, uint32_t *value)
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{
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uint32_t *addr;
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WARN_ON(seg);
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/* Use the hardware mechanism for non-simulated devices */
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if (!is_simulated(bus, devfn))
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return pci_direct_conf1.read(seg, bus, devfn, reg, len, value);
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/*
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* No device has config registers past 0x70, so we save table space
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* by not storing entries for the nonexistent registers
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*/
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if (reg >= 0x70)
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addr = &zero_loc;
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else {
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switch (devfn) {
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case 0x8:
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addr = hdr_addr(is_lx ? lxnb_hdr : gxnb_hdr, reg);
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break;
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case 0x9:
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addr = hdr_addr(is_lx ? lxfb_hdr : gxfb_hdr, reg);
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break;
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case 0xa:
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addr = is_lx ? hdr_addr(aes_hdr, reg) : &ff_loc;
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break;
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case 0x78:
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addr = hdr_addr(isa_hdr, reg);
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break;
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case 0x7b:
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addr = hdr_addr(ac97_hdr, reg);
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break;
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case 0x7c:
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addr = hdr_addr(ohci_hdr, reg);
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break;
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case 0x7d:
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addr = hdr_addr(ehci_hdr, reg);
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break;
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default:
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addr = &ff_loc;
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break;
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}
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}
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switch (len) {
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case 1:
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*value = *(uint8_t *)addr;
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break;
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case 2:
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*value = *(uint16_t *)addr;
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break;
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case 4:
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*value = *addr;
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break;
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default:
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BUG();
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}
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return 0;
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}
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static int pci_olpc_write(unsigned int seg, unsigned int bus,
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unsigned int devfn, int reg, int len, uint32_t value)
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{
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WARN_ON(seg);
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/* Use the hardware mechanism for non-simulated devices */
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if (!is_simulated(bus, devfn))
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return pci_direct_conf1.write(seg, bus, devfn, reg, len, value);
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/* XXX we may want to extend this to simulate EHCI power management */
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/*
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* Mostly we just discard writes, but if the write is a size probe
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* (i.e. writing ~0 to a BAR), we remember it and arrange to return
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* the appropriate size mask on the next read. This is cheating
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* to some extent, because it depends on the fact that the next
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* access after such a write will always be a read to the same BAR.
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*/
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if ((reg >= 0x10) && (reg < 0x2c)) {
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/* write is to a BAR */
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if (value == ~0)
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bar_probing = 1;
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} else {
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/*
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* No warning on writes to ROM BAR, CMD, LATENCY_TIMER,
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* CACHE_LINE_SIZE, or PM registers.
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*/
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if ((reg != PCI_ROM_ADDRESS) && (reg != PCI_COMMAND_MASTER) &&
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(reg != PCI_LATENCY_TIMER) &&
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(reg != PCI_CACHE_LINE_SIZE) && (reg != 0x44))
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printk(KERN_WARNING "OLPC PCI: Config write to devfn"
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" %x reg %x value %x\n", devfn, reg, value);
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}
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return 0;
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}
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static const struct pci_raw_ops pci_olpc_conf = {
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.read = pci_olpc_read,
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.write = pci_olpc_write,
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};
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int __init pci_olpc_init(void)
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{
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printk(KERN_INFO "PCI: Using configuration type OLPC XO-1\n");
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raw_pci_ops = &pci_olpc_conf;
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is_lx = is_geode_lx();
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return 0;
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}
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