51533b615e
New CRIS sub architecture named v32. From: Dave Jones <davej@redhat.com> Fix swapped kmalloc args Signed-off-by: Mikael Starvik <starvik@axis.com> Signed-off-by: Dave Jones <davej@redhat.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
70 lines
2.3 KiB
C
70 lines
2.3 KiB
C
#ifndef __irq_nmi_defs_asm_h
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#define __irq_nmi_defs_asm_h
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/*
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* This file is autogenerated from
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* file: ../../mod/irq_nmi.r
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* id: <not found>
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* last modfied: Thu Jan 22 09:22:43 2004
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*
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* by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/irq_nmi_defs_asm.h ../../mod/irq_nmi.r
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* id: $Id: irq_nmi_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
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* Any changes here will be lost.
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*
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* -*- buffer-read-only: t -*-
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*/
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#ifndef REG_FIELD
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#define REG_FIELD( scope, reg, field, value ) \
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REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
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#define REG_FIELD_X_( value, shift ) ((value) << shift)
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#endif
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#ifndef REG_STATE
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#define REG_STATE( scope, reg, field, symbolic_value ) \
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REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
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#define REG_STATE_X_( k, shift ) (k << shift)
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#endif
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#ifndef REG_MASK
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#define REG_MASK( scope, reg, field ) \
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REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
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#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
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#endif
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#ifndef REG_LSB
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#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
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#endif
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#ifndef REG_BIT
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#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
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#endif
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#ifndef REG_ADDR
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#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
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#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
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#endif
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#ifndef REG_ADDR_VECT
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#define REG_ADDR_VECT( scope, inst, reg, index ) \
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REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
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STRIDE_##scope##_##reg )
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#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
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((inst) + offs + (index) * stride)
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#endif
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/* Register rw_cmd, scope irq_nmi, type rw */
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#define reg_irq_nmi_rw_cmd___delay___lsb 0
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#define reg_irq_nmi_rw_cmd___delay___width 16
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#define reg_irq_nmi_rw_cmd___op___lsb 16
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#define reg_irq_nmi_rw_cmd___op___width 2
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#define reg_irq_nmi_rw_cmd_offset 0
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/* Constants */
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#define regk_irq_nmi_ack_irq 0x00000002
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#define regk_irq_nmi_ack_nmi 0x00000003
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#define regk_irq_nmi_irq 0x00000000
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#define regk_irq_nmi_nmi 0x00000001
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#endif /* __irq_nmi_defs_asm_h */
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