031bd879f7
ARM v7 architecture introduced the concept of cache levels and related control registers. New processors like A7 and A15 embed an L2 unified cache controller that becomes part of the cache level hierarchy. Some operations in the kernel like cpu_suspend and __cpu_disable do not require a flush of the entire cache hierarchy to DRAM but just the cache levels belonging to the Level of Unification Inner Shareable (LoUIS), which in most of ARM v7 systems correspond to L1. The current cache flushing API used in cpu_suspend and __cpu_disable, flush_cache_all(), ends up flushing the whole cache hierarchy since for v7 it cleans and invalidates all cache levels up to Level of Coherency (LoC) which cripples system performance when used in hot paths like hotplug and cpuidle. Therefore a new kernel cache maintenance API must be added to cope with latest ARM system requirements. This patch adds flush_cache_louis() to the ARM kernel cache maintenance API. This function cleans and invalidates all data cache levels up to the Level of Unification Inner Shareable (LoUIS) and invalidates the instruction cache for processors that support it (> v7). This patch also creates an alias of the cache LoUIS function to flush_kern_all for all processor versions prior to v7, so that the current cache flushing behaviour is unchanged for those processors. v7 cache maintenance code implements a cache LoUIS function that cleans and invalidates the D-cache up to LoUIS and invalidates the I-cache, according to the new API. Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Reviewed-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: Shawn Guo <shawn.guo@linaro.org>
505 lines
13 KiB
ArmAsm
505 lines
13 KiB
ArmAsm
/*
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* linux/arch/arm/mm/proc-arm926.S: MMU functions for ARM926EJ-S
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*
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* Copyright (C) 1999-2001 ARM Limited
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* Copyright (C) 2000 Deep Blue Solutions Ltd.
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* hacked for non-paged-MM by Hyok S. Choi, 2003.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*
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* These are the low level assembler for performing cache and TLB
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* functions on the arm926.
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*
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* CONFIG_CPU_ARM926_CPU_IDLE -> nohlt
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/assembler.h>
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#include <asm/hwcap.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/pgtable.h>
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#include <asm/page.h>
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#include <asm/ptrace.h>
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#include "proc-macros.S"
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/*
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* This is the maximum size of an area which will be invalidated
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* using the single invalidate entry instructions. Anything larger
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* than this, and we go for the whole cache.
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*
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* This value should be chosen such that we choose the cheapest
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* alternative.
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*/
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#define CACHE_DLIMIT 16384
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/*
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* the cache line size of the I and D cache
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*/
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#define CACHE_DLINESIZE 32
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.text
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/*
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* cpu_arm926_proc_init()
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*/
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ENTRY(cpu_arm926_proc_init)
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mov pc, lr
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/*
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* cpu_arm926_proc_fin()
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*/
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ENTRY(cpu_arm926_proc_fin)
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mrc p15, 0, r0, c1, c0, 0 @ ctrl register
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bic r0, r0, #0x1000 @ ...i............
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bic r0, r0, #0x000e @ ............wca.
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mcr p15, 0, r0, c1, c0, 0 @ disable caches
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mov pc, lr
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/*
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* cpu_arm926_reset(loc)
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*
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* Perform a soft reset of the system. Put the CPU into the
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* same state as it would be if it had been reset, and branch
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* to what would be the reset vector.
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*
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* loc: location to jump to for soft reset
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*/
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.align 5
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.pushsection .idmap.text, "ax"
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ENTRY(cpu_arm926_reset)
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mov ip, #0
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mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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#ifdef CONFIG_MMU
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mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
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#endif
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mrc p15, 0, ip, c1, c0, 0 @ ctrl register
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bic ip, ip, #0x000f @ ............wcam
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bic ip, ip, #0x1100 @ ...i...s........
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mcr p15, 0, ip, c1, c0, 0 @ ctrl register
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mov pc, r0
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ENDPROC(cpu_arm926_reset)
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.popsection
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/*
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* cpu_arm926_do_idle()
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*
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* Called with IRQs disabled
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*/
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.align 10
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ENTRY(cpu_arm926_do_idle)
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mov r0, #0
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mrc p15, 0, r1, c1, c0, 0 @ Read control register
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mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
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bic r2, r1, #1 << 12
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mrs r3, cpsr @ Disable FIQs while Icache
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orr ip, r3, #PSR_F_BIT @ is disabled
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msr cpsr_c, ip
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mcr p15, 0, r2, c1, c0, 0 @ Disable I cache
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mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
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mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable
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msr cpsr_c, r3 @ Restore FIQ state
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mov pc, lr
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/*
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* flush_icache_all()
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*
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* Unconditionally clean and invalidate the entire icache.
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*/
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ENTRY(arm926_flush_icache_all)
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
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mov pc, lr
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ENDPROC(arm926_flush_icache_all)
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/*
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* flush_user_cache_all()
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*
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* Clean and invalidate all cache entries in a particular
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* address space.
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*/
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ENTRY(arm926_flush_user_cache_all)
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/* FALLTHROUGH */
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/*
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* flush_kern_cache_all()
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*
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* Clean and invalidate the entire cache.
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*/
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ENTRY(arm926_flush_kern_cache_all)
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mov r2, #VM_EXEC
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mov ip, #0
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__flush_whole_cache:
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#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
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mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
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#else
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1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
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bne 1b
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#endif
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tst r2, #VM_EXEC
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mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
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mcrne p15, 0, ip, c7, c10, 4 @ drain WB
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mov pc, lr
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/*
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* flush_user_cache_range(start, end, flags)
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*
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* Clean and invalidate a range of cache entries in the
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* specified address range.
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*
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* - start - start address (inclusive)
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* - end - end address (exclusive)
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* - flags - vm_flags describing address space
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*/
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ENTRY(arm926_flush_user_cache_range)
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mov ip, #0
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sub r3, r1, r0 @ calculate total size
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cmp r3, #CACHE_DLIMIT
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bgt __flush_whole_cache
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1: tst r2, #VM_EXEC
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#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
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mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
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mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
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add r0, r0, #CACHE_DLINESIZE
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mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
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mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
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add r0, r0, #CACHE_DLINESIZE
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#else
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mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
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mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
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add r0, r0, #CACHE_DLINESIZE
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mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
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mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
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add r0, r0, #CACHE_DLINESIZE
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#endif
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cmp r0, r1
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blo 1b
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tst r2, #VM_EXEC
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mcrne p15, 0, ip, c7, c10, 4 @ drain WB
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mov pc, lr
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/*
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* coherent_kern_range(start, end)
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*
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* Ensure coherency between the Icache and the Dcache in the
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* region described by start, end. If you have non-snooping
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* Harvard caches, you need to implement this function.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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ENTRY(arm926_coherent_kern_range)
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/* FALLTHROUGH */
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/*
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* coherent_user_range(start, end)
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*
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* Ensure coherency between the Icache and the Dcache in the
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* region described by start, end. If you have non-snooping
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* Harvard caches, you need to implement this function.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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ENTRY(arm926_coherent_user_range)
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bic r0, r0, #CACHE_DLINESIZE - 1
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mov r0, #0
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mov pc, lr
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/*
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* flush_kern_dcache_area(void *addr, size_t size)
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*
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* Ensure no D cache aliasing occurs, either with itself or
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* the I cache
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*
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* - addr - kernel address
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* - size - region size
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*/
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ENTRY(arm926_flush_kern_dcache_area)
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add r1, r0, r1
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1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mov pc, lr
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/*
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* dma_inv_range(start, end)
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*
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* Invalidate (discard) the specified virtual address range.
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* May not write back any entries. If 'start' or 'end'
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* are not cache line aligned, those lines must be written
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* back.
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*
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* - start - virtual start address
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* - end - virtual end address
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*
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* (same as v4wb)
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*/
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arm926_dma_inv_range:
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#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
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tst r0, #CACHE_DLINESIZE - 1
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mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
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tst r1, #CACHE_DLINESIZE - 1
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mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
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#endif
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bic r0, r0, #CACHE_DLINESIZE - 1
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1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mov pc, lr
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/*
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* dma_clean_range(start, end)
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*
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* Clean the specified virtual address range.
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*
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* - start - virtual start address
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* - end - virtual end address
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*
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* (same as v4wb)
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*/
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arm926_dma_clean_range:
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#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
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bic r0, r0, #CACHE_DLINESIZE - 1
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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#endif
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mov pc, lr
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/*
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* dma_flush_range(start, end)
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*
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* Clean and invalidate the specified virtual address range.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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ENTRY(arm926_dma_flush_range)
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bic r0, r0, #CACHE_DLINESIZE - 1
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1:
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#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
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mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
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#else
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mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
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#endif
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mov pc, lr
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/*
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* dma_map_area(start, size, dir)
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* - start - kernel virtual start address
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* - size - size of region
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* - dir - DMA direction
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*/
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ENTRY(arm926_dma_map_area)
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add r1, r1, r0
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cmp r2, #DMA_TO_DEVICE
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beq arm926_dma_clean_range
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bcs arm926_dma_inv_range
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b arm926_dma_flush_range
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ENDPROC(arm926_dma_map_area)
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/*
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* dma_unmap_area(start, size, dir)
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* - start - kernel virtual start address
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* - size - size of region
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* - dir - DMA direction
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*/
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ENTRY(arm926_dma_unmap_area)
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mov pc, lr
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ENDPROC(arm926_dma_unmap_area)
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.globl arm926_flush_kern_cache_louis
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.equ arm926_flush_kern_cache_louis, arm926_flush_kern_cache_all
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@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
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define_cache_functions arm926
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ENTRY(cpu_arm926_dcache_clean_area)
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#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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add r0, r0, #CACHE_DLINESIZE
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subs r1, r1, #CACHE_DLINESIZE
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bhi 1b
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#endif
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mov pc, lr
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/* =============================== PageTable ============================== */
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/*
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* cpu_arm926_switch_mm(pgd)
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*
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* Set the translation base pointer to be as described by pgd.
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*
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* pgd: new page tables
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*/
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.align 5
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ENTRY(cpu_arm926_switch_mm)
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#ifdef CONFIG_MMU
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mov ip, #0
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#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
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mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
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#else
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@ && 'Clean & Invalidate whole DCache'
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1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
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bne 1b
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#endif
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mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
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mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
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#endif
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mov pc, lr
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/*
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* cpu_arm926_set_pte_ext(ptep, pte, ext)
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*
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* Set a PTE and flush it out
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*/
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.align 5
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ENTRY(cpu_arm926_set_pte_ext)
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#ifdef CONFIG_MMU
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armv3_set_pte_ext
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mov r0, r0
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#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
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mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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#endif
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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#endif
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mov pc, lr
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/* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */
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.globl cpu_arm926_suspend_size
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.equ cpu_arm926_suspend_size, 4 * 3
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#ifdef CONFIG_PM_SLEEP
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ENTRY(cpu_arm926_do_suspend)
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stmfd sp!, {r4 - r6, lr}
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mrc p15, 0, r4, c13, c0, 0 @ PID
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mrc p15, 0, r5, c3, c0, 0 @ Domain ID
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mrc p15, 0, r6, c1, c0, 0 @ Control register
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stmia r0, {r4 - r6}
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ldmfd sp!, {r4 - r6, pc}
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ENDPROC(cpu_arm926_do_suspend)
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ENTRY(cpu_arm926_do_resume)
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mov ip, #0
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mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs
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mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches
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ldmia r0, {r4 - r6}
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mcr p15, 0, r4, c13, c0, 0 @ PID
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mcr p15, 0, r5, c3, c0, 0 @ Domain ID
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mcr p15, 0, r1, c2, c0, 0 @ TTB address
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mov r0, r6 @ control register
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b cpu_resume_mmu
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ENDPROC(cpu_arm926_do_resume)
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#endif
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__CPUINIT
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.type __arm926_setup, #function
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__arm926_setup:
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mov r0, #0
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mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
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mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
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#ifdef CONFIG_MMU
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mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
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#endif
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#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
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mov r0, #4 @ disable write-back on caches explicitly
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mcr p15, 7, r0, c15, c0, 0
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#endif
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adr r5, arm926_crval
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ldmia r5, {r5, r6}
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mrc p15, 0, r0, c1, c0 @ get control register v4
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bic r0, r0, r5
|
|
orr r0, r0, r6
|
|
#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
|
|
orr r0, r0, #0x4000 @ .1.. .... .... ....
|
|
#endif
|
|
mov pc, lr
|
|
.size __arm926_setup, . - __arm926_setup
|
|
|
|
/*
|
|
* R
|
|
* .RVI ZFRS BLDP WCAM
|
|
* .011 0001 ..11 0101
|
|
*
|
|
*/
|
|
.type arm926_crval, #object
|
|
arm926_crval:
|
|
crval clear=0x00007f3f, mmuset=0x00003135, ucset=0x00001134
|
|
|
|
__INITDATA
|
|
|
|
@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
|
|
define_processor_functions arm926, dabort=v5tj_early_abort, pabort=legacy_pabort, suspend=1
|
|
|
|
.section ".rodata"
|
|
|
|
string cpu_arch_name, "armv5tej"
|
|
string cpu_elf_name, "v5"
|
|
string cpu_arm926_name, "ARM926EJ-S"
|
|
|
|
.align
|
|
|
|
.section ".proc.info.init", #alloc, #execinstr
|
|
|
|
.type __arm926_proc_info,#object
|
|
__arm926_proc_info:
|
|
.long 0x41069260 @ ARM926EJ-S (v5TEJ)
|
|
.long 0xff0ffff0
|
|
.long PMD_TYPE_SECT | \
|
|
PMD_SECT_BUFFERABLE | \
|
|
PMD_SECT_CACHEABLE | \
|
|
PMD_BIT4 | \
|
|
PMD_SECT_AP_WRITE | \
|
|
PMD_SECT_AP_READ
|
|
.long PMD_TYPE_SECT | \
|
|
PMD_BIT4 | \
|
|
PMD_SECT_AP_WRITE | \
|
|
PMD_SECT_AP_READ
|
|
b __arm926_setup
|
|
.long cpu_arch_name
|
|
.long cpu_elf_name
|
|
.long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA
|
|
.long cpu_arm926_name
|
|
.long arm926_processor_functions
|
|
.long v4wbi_tlb_fns
|
|
.long v4wb_user_fns
|
|
.long arm926_cache_fns
|
|
.size __arm926_proc_info, . - __arm926_proc_info
|