bff06d5522
Instead of all of this cpu-specific code to remap the kernel
to the correct location, use portable firmware calls to do
this instead.
What we do now is the following in position independant
assembler:
chosen_node = prom_finddevice("/chosen");
prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu");
vaddr = 4MB_ALIGN(current_text_addr());
prom_translate(vaddr, &paddr_high, &paddr_low, &mode);
prom_boot_mapping_mode = mode;
prom_boot_mapping_phys_high = paddr_high;
prom_boot_mapping_phys_low = paddr_low;
prom_map(-1, 8 * 1024 * 1024, KERNBASE, paddr_low);
and that replaces the massive amount of by-hand TLB probing and
programming we used to do here.
The new code should also handle properly the case where the kernel
is mapped at the correct address already (think: future kexec
support).
Consequently, the bulk of remap_kernel() dies as does the entirety
of arch/sparc64/prom/map.S
We try to share some strings in the PROM library with the ones used
at bootup, and while we're here mark input strings to oplib.h routines
with "const" when appropriate.
There are many more simplifications now possible. For one thing, we
can consolidate the two copies we now have of a lot of cpu setup code
sitting in head.S and trampoline.S.
This is a significant step towards CONFIG_DEBUG_PAGEALLOC support.
Signed-off-by: David S. Miller <davem@davemloft.net>
554 lines
13 KiB
ArmAsm
554 lines
13 KiB
ArmAsm
/* $Id: head.S,v 1.87 2002/02/09 19:49:31 davem Exp $
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* head.S: Initial boot code for the Sparc64 port of Linux.
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*
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* Copyright (C) 1996,1997 David S. Miller (davem@caip.rutgers.edu)
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* Copyright (C) 1996 David Sitsky (David.Sitsky@anu.edu.au)
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* Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
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* Copyright (C) 1997 Miguel de Icaza (miguel@nuclecu.unam.mx)
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*/
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#include <linux/config.h>
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#include <linux/version.h>
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#include <linux/errno.h>
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#include <asm/thread_info.h>
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#include <asm/asi.h>
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#include <asm/pstate.h>
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#include <asm/ptrace.h>
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#include <asm/spitfire.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/errno.h>
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#include <asm/signal.h>
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#include <asm/processor.h>
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#include <asm/lsu.h>
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#include <asm/dcr.h>
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#include <asm/dcu.h>
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#include <asm/head.h>
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#include <asm/ttable.h>
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#include <asm/mmu.h>
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/* This section from from _start to sparc64_boot_end should fit into
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* 0x0000.0000.0040.4000 to 0x0000.0000.0040.8000 and will be sharing space
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* with bootup_user_stack, which is from 0x0000.0000.0040.4000 to
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* 0x0000.0000.0040.6000 and empty_bad_page, which is from
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* 0x0000.0000.0040.6000 to 0x0000.0000.0040.8000.
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*/
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.text
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.globl start, _start, stext, _stext
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_start:
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start:
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_stext:
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stext:
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bootup_user_stack:
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! 0x0000000000404000
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b sparc64_boot
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flushw /* Flush register file. */
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/* This stuff has to be in sync with SILO and other potential boot loaders
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* Fields should be kept upward compatible and whenever any change is made,
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* HdrS version should be incremented.
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*/
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.global root_flags, ram_flags, root_dev
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.global sparc_ramdisk_image, sparc_ramdisk_size
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.global sparc_ramdisk_image64
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.ascii "HdrS"
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.word LINUX_VERSION_CODE
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/* History:
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*
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* 0x0300 : Supports being located at other than 0x4000
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* 0x0202 : Supports kernel params string
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* 0x0201 : Supports reboot_command
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*/
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.half 0x0301 /* HdrS version */
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root_flags:
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.half 1
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root_dev:
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.half 0
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ram_flags:
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.half 0
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sparc_ramdisk_image:
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.word 0
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sparc_ramdisk_size:
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.word 0
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.xword reboot_command
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.xword bootstr_info
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sparc_ramdisk_image64:
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.xword 0
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.word _end
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/* PROM cif handler code address is in %o4. */
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sparc64_boot:
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1: rd %pc, %g7
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set 1b, %g1
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cmp %g1, %g7
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be,pn %xcc, sparc64_boot_after_remap
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mov %o4, %l7
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/* We need to remap the kernel. Use position independant
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* code to remap us to KERNBASE.
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*
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* SILO can invoke us with 32-bit address masking enabled,
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* so make sure that's clear.
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*/
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rdpr %pstate, %g1
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andn %g1, PSTATE_AM, %g1
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wrpr %g1, 0x0, %pstate
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ba,a,pt %xcc, 1f
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.globl prom_finddev_name, prom_chosen_path
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.globl prom_getprop_name, prom_mmu_name
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.globl prom_callmethod_name, prom_translate_name
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.globl prom_map_name, prom_unmap_name, prom_mmu_ihandle_cache
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.globl prom_boot_mapped_pc, prom_boot_mapping_mode
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.globl prom_boot_mapping_phys_high, prom_boot_mapping_phys_low
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prom_finddev_name:
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.asciz "finddevice"
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prom_chosen_path:
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.asciz "/chosen"
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prom_getprop_name:
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.asciz "getprop"
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prom_mmu_name:
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.asciz "mmu"
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prom_callmethod_name:
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.asciz "call-method"
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prom_translate_name:
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.asciz "translate"
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prom_map_name:
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.asciz "map"
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prom_unmap_name:
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.asciz "unmap"
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.align 4
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prom_mmu_ihandle_cache:
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.word 0
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prom_boot_mapped_pc:
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.word 0
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prom_boot_mapping_mode:
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.word 0
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.align 8
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prom_boot_mapping_phys_high:
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.xword 0
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prom_boot_mapping_phys_low:
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.xword 0
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1:
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rd %pc, %l0
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mov (1b - prom_finddev_name), %l1
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mov (1b - prom_chosen_path), %l2
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mov (1b - prom_boot_mapped_pc), %l3
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sub %l0, %l1, %l1
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sub %l0, %l2, %l2
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sub %l0, %l3, %l3
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stw %l0, [%l3]
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sub %sp, (192 + 128), %sp
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/* chosen_node = prom_finddevice("/chosen") */
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stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "finddevice"
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mov 1, %l3
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stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 1
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stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
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stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1, "/chosen"
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stx %g0, [%sp + 2047 + 128 + 0x20] ! ret1
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call %l7
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add %sp, (2047 + 128), %o0 ! argument array
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ldx [%sp + 2047 + 128 + 0x20], %l4 ! chosen device node
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mov (1b - prom_getprop_name), %l1
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mov (1b - prom_mmu_name), %l2
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mov (1b - prom_mmu_ihandle_cache), %l5
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sub %l0, %l1, %l1
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sub %l0, %l2, %l2
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sub %l0, %l5, %l5
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/* prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu") */
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stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "getprop"
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mov 4, %l3
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stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 4
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mov 1, %l3
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stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
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stx %l4, [%sp + 2047 + 128 + 0x18] ! arg1, chosen_node
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stx %l2, [%sp + 2047 + 128 + 0x20] ! arg2, "mmu"
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stx %l5, [%sp + 2047 + 128 + 0x28] ! arg3, &prom_mmu_ihandle_cache
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mov 4, %l3
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stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4, sizeof(arg3)
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stx %g0, [%sp + 2047 + 128 + 0x38] ! ret1
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call %l7
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add %sp, (2047 + 128), %o0 ! argument array
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mov (1b - prom_callmethod_name), %l1
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mov (1b - prom_translate_name), %l2
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sub %l0, %l1, %l1
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sub %l0, %l2, %l2
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lduw [%l5], %l5 ! prom_mmu_ihandle_cache
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stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "call-method"
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mov 3, %l3
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stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 3
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mov 5, %l3
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stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 5
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stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1: "translate"
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stx %l5, [%sp + 2047 + 128 + 0x20] ! arg2: prom_mmu_ihandle_cache
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srlx %l0, 22, %l3
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sllx %l3, 22, %l3
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stx %l3, [%sp + 2047 + 128 + 0x28] ! arg3: vaddr, our PC
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stx %g0, [%sp + 2047 + 128 + 0x30] ! res1
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stx %g0, [%sp + 2047 + 128 + 0x38] ! res2
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stx %g0, [%sp + 2047 + 128 + 0x40] ! res3
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stx %g0, [%sp + 2047 + 128 + 0x48] ! res4
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stx %g0, [%sp + 2047 + 128 + 0x50] ! res5
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call %l7
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add %sp, (2047 + 128), %o0 ! argument array
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ldx [%sp + 2047 + 128 + 0x40], %l1 ! translation mode
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mov (1b - prom_boot_mapping_mode), %l4
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sub %l0, %l4, %l4
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stw %l1, [%l4]
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mov (1b - prom_boot_mapping_phys_high), %l4
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sub %l0, %l4, %l4
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ldx [%sp + 2047 + 128 + 0x48], %l2 ! physaddr high
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stx %l2, [%l4 + 0x0]
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ldx [%sp + 2047 + 128 + 0x50], %l3 ! physaddr low
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stx %l3, [%l4 + 0x8]
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/* Leave service as-is, "call-method" */
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mov 7, %l3
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stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 7
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mov 1, %l3
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stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 7
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mov (1b - prom_map_name), %l3
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sub %l0, %l3, %l3
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stx %l3, [%sp + 2047 + 128 + 0x18] ! arg1: "map"
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/* Leave arg2 as-is, prom_mmu_ihandle_cache */
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mov -1, %l3
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stx %l3, [%sp + 2047 + 128 + 0x28] ! arg3: mode (-1 default)
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sethi %hi(8 * 1024 * 1024), %l3
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stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4: size (8MB)
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sethi %hi(KERNBASE), %l3
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stx %l3, [%sp + 2047 + 128 + 0x38] ! arg5: vaddr (KERNBASE)
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stx %g0, [%sp + 2047 + 128 + 0x40] ! arg6: empty
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mov (1b - prom_boot_mapping_phys_low), %l3
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sub %l0, %l3, %l3
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ldx [%l3], %l3
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stx %l3, [%sp + 2047 + 128 + 0x48] ! arg7: phys addr
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call %l7
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add %sp, (2047 + 128), %o0 ! argument array
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add %sp, (192 + 128), %sp
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sparc64_boot_after_remap:
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BRANCH_IF_CHEETAH_BASE(g1,g7,cheetah_boot)
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BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,cheetah_plus_boot)
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ba,pt %xcc, spitfire_boot
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nop
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cheetah_plus_boot:
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/* Preserve OBP chosen DCU and DCR register settings. */
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ba,pt %xcc, cheetah_generic_boot
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nop
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cheetah_boot:
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mov DCR_BPE | DCR_RPE | DCR_SI | DCR_IFPOE | DCR_MS, %g1
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wr %g1, %asr18
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sethi %uhi(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g7
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or %g7, %ulo(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g7
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sllx %g7, 32, %g7
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or %g7, DCU_DM | DCU_IM | DCU_DC | DCU_IC, %g7
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stxa %g7, [%g0] ASI_DCU_CONTROL_REG
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membar #Sync
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cheetah_generic_boot:
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mov TSB_EXTENSION_P, %g3
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stxa %g0, [%g3] ASI_DMMU
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stxa %g0, [%g3] ASI_IMMU
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membar #Sync
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mov TSB_EXTENSION_S, %g3
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stxa %g0, [%g3] ASI_DMMU
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membar #Sync
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mov TSB_EXTENSION_N, %g3
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stxa %g0, [%g3] ASI_DMMU
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stxa %g0, [%g3] ASI_IMMU
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membar #Sync
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ba,a,pt %xcc, jump_to_sun4u_init
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spitfire_boot:
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/* Typically PROM has already enabled both MMU's and both on-chip
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* caches, but we do it here anyway just to be paranoid.
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*/
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mov (LSU_CONTROL_IC|LSU_CONTROL_DC|LSU_CONTROL_IM|LSU_CONTROL_DM), %g1
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stxa %g1, [%g0] ASI_LSU_CONTROL
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membar #Sync
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jump_to_sun4u_init:
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/*
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* Make sure we are in privileged mode, have address masking,
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* using the ordinary globals and have enabled floating
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* point.
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*
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* Again, typically PROM has left %pil at 13 or similar, and
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* (PSTATE_PRIV | PSTATE_PEF | PSTATE_IE) in %pstate.
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*/
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wrpr %g0, (PSTATE_PRIV|PSTATE_PEF|PSTATE_IE), %pstate
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wr %g0, 0, %fprs
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set sun4u_init, %g2
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jmpl %g2 + %g0, %g0
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nop
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sun4u_init:
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/* Set ctx 0 */
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mov PRIMARY_CONTEXT, %g7
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stxa %g0, [%g7] ASI_DMMU
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membar #Sync
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mov SECONDARY_CONTEXT, %g7
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stxa %g0, [%g7] ASI_DMMU
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membar #Sync
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BRANCH_IF_ANY_CHEETAH(g1,g7,cheetah_tlb_fixup)
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ba,pt %xcc, spitfire_tlb_fixup
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nop
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cheetah_tlb_fixup:
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mov 2, %g2 /* Set TLB type to cheetah+. */
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BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,1f)
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mov 1, %g2 /* Set TLB type to cheetah. */
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1: sethi %hi(tlb_type), %g1
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stw %g2, [%g1 + %lo(tlb_type)]
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BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,1f)
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ba,pt %xcc, 2f
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nop
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1: /* Patch context register writes to support nucleus page
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* size correctly.
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*/
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call cheetah_plus_patch_etrap
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nop
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call cheetah_plus_patch_rtrap
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nop
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call cheetah_plus_patch_fpdis
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nop
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call cheetah_plus_patch_winfixup
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nop
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2: /* Patch copy/page operations to cheetah optimized versions. */
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call cheetah_patch_copyops
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nop
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call cheetah_patch_copy_page
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nop
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call cheetah_patch_cachetlbops
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nop
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ba,pt %xcc, tlb_fixup_done
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nop
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spitfire_tlb_fixup:
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/* Set TLB type to spitfire. */
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mov 0, %g2
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sethi %hi(tlb_type), %g1
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stw %g2, [%g1 + %lo(tlb_type)]
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tlb_fixup_done:
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sethi %hi(init_thread_union), %g6
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or %g6, %lo(init_thread_union), %g6
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ldx [%g6 + TI_TASK], %g4
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mov %sp, %l6
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mov %o4, %l7
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wr %g0, ASI_P, %asi
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mov 1, %g1
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sllx %g1, THREAD_SHIFT, %g1
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sub %g1, (STACKFRAME_SZ + STACK_BIAS), %g1
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add %g6, %g1, %sp
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mov 0, %fp
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/* Set per-cpu pointer initially to zero, this makes
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* the boot-cpu use the in-kernel-image per-cpu areas
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* before setup_per_cpu_area() is invoked.
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*/
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clr %g5
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wrpr %g0, 0, %wstate
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wrpr %g0, 0x0, %tl
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/* Clear the bss */
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sethi %hi(__bss_start), %o0
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or %o0, %lo(__bss_start), %o0
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sethi %hi(_end), %o1
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or %o1, %lo(_end), %o1
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call __bzero
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sub %o1, %o0, %o1
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mov %l6, %o1 ! OpenPROM stack
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call prom_init
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mov %l7, %o0 ! OpenPROM cif handler
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/* Off we go.... */
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call start_kernel
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nop
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/* Not reached... */
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/* IMPORTANT NOTE: Whenever making changes here, check
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* trampoline.S as well. -jj */
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.globl setup_tba
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setup_tba: /* i0 = is_starfire */
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save %sp, -160, %sp
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rdpr %tba, %g7
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sethi %hi(prom_tba), %o1
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or %o1, %lo(prom_tba), %o1
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stx %g7, [%o1]
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/* Setup "Linux" globals 8-) */
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rdpr %pstate, %o1
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mov %g6, %o2
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wrpr %o1, (PSTATE_AG|PSTATE_IE), %pstate
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sethi %hi(sparc64_ttable_tl0), %g1
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wrpr %g1, %tba
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mov %o2, %g6
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/* Set up MMU globals */
|
|
wrpr %o1, (PSTATE_MG|PSTATE_IE), %pstate
|
|
|
|
/* Set fixed globals used by dTLB miss handler. */
|
|
#define KERN_HIGHBITS ((_PAGE_VALID|_PAGE_SZ4MB)^0xfffff80000000000)
|
|
#define KERN_LOWBITS (_PAGE_CP | _PAGE_CV | _PAGE_P | _PAGE_W)
|
|
|
|
mov TSB_REG, %g1
|
|
stxa %g0, [%g1] ASI_DMMU
|
|
membar #Sync
|
|
stxa %g0, [%g1] ASI_IMMU
|
|
membar #Sync
|
|
mov TLB_SFSR, %g1
|
|
sethi %uhi(KERN_HIGHBITS), %g2
|
|
or %g2, %ulo(KERN_HIGHBITS), %g2
|
|
sllx %g2, 32, %g2
|
|
or %g2, KERN_LOWBITS, %g2
|
|
|
|
BRANCH_IF_ANY_CHEETAH(g3,g7,cheetah_vpte_base)
|
|
ba,pt %xcc, spitfire_vpte_base
|
|
nop
|
|
|
|
cheetah_vpte_base:
|
|
sethi %uhi(VPTE_BASE_CHEETAH), %g3
|
|
or %g3, %ulo(VPTE_BASE_CHEETAH), %g3
|
|
ba,pt %xcc, 2f
|
|
sllx %g3, 32, %g3
|
|
|
|
spitfire_vpte_base:
|
|
sethi %uhi(VPTE_BASE_SPITFIRE), %g3
|
|
or %g3, %ulo(VPTE_BASE_SPITFIRE), %g3
|
|
sllx %g3, 32, %g3
|
|
|
|
2:
|
|
clr %g7
|
|
#undef KERN_HIGHBITS
|
|
#undef KERN_LOWBITS
|
|
|
|
/* Kill PROM timer */
|
|
sethi %hi(0x80000000), %o2
|
|
sllx %o2, 32, %o2
|
|
wr %o2, 0, %tick_cmpr
|
|
|
|
BRANCH_IF_ANY_CHEETAH(o2,o3,1f)
|
|
|
|
ba,pt %xcc, 2f
|
|
nop
|
|
|
|
/* Disable STICK_INT interrupts. */
|
|
1:
|
|
sethi %hi(0x80000000), %o2
|
|
sllx %o2, 32, %o2
|
|
wr %o2, %asr25
|
|
|
|
/* Ok, we're done setting up all the state our trap mechanims needs,
|
|
* now get back into normal globals and let the PROM know what is up.
|
|
*/
|
|
2:
|
|
wrpr %g0, %g0, %wstate
|
|
wrpr %o1, PSTATE_IE, %pstate
|
|
|
|
call init_irqwork_curcpu
|
|
nop
|
|
|
|
call prom_set_trap_table
|
|
sethi %hi(sparc64_ttable_tl0), %o0
|
|
|
|
BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g2,g3,1f)
|
|
ba,pt %xcc, 2f
|
|
nop
|
|
|
|
1: /* Start using proper page size encodings in ctx register. */
|
|
sethi %uhi(CTX_CHEETAH_PLUS_NUC), %g3
|
|
mov PRIMARY_CONTEXT, %g1
|
|
sllx %g3, 32, %g3
|
|
sethi %hi(CTX_CHEETAH_PLUS_CTX0), %g2
|
|
or %g3, %g2, %g3
|
|
stxa %g3, [%g1] ASI_DMMU
|
|
membar #Sync
|
|
|
|
2:
|
|
rdpr %pstate, %o1
|
|
or %o1, PSTATE_IE, %o1
|
|
wrpr %o1, 0, %pstate
|
|
|
|
ret
|
|
restore
|
|
|
|
/*
|
|
* The following skips make sure the trap table in ttable.S is aligned
|
|
* on a 32K boundary as required by the v9 specs for TBA register.
|
|
*/
|
|
sparc64_boot_end:
|
|
.skip 0x2000 + _start - sparc64_boot_end
|
|
bootup_user_stack_end:
|
|
.skip 0x2000
|
|
|
|
#ifdef CONFIG_SBUS
|
|
/* This is just a hack to fool make depend config.h discovering
|
|
strategy: As the .S files below need config.h, but
|
|
make depend does not find it for them, we include config.h
|
|
in head.S */
|
|
#endif
|
|
|
|
! 0x0000000000408000
|
|
|
|
#include "ttable.S"
|
|
#include "systbls.S"
|
|
|
|
.align 1024
|
|
.globl swapper_pg_dir
|
|
swapper_pg_dir:
|
|
.word 0
|
|
|
|
#include "ktlb.S"
|
|
#include "etrap.S"
|
|
#include "rtrap.S"
|
|
#include "winfixup.S"
|
|
#include "entry.S"
|
|
|
|
/* This is just anal retentiveness on my part... */
|
|
.align 16384
|
|
|
|
.data
|
|
.align 8
|
|
.globl prom_tba, tlb_type
|
|
prom_tba: .xword 0
|
|
tlb_type: .word 0 /* Must NOT end up in BSS */
|
|
.section ".fixup",#alloc,#execinstr
|
|
.globl __ret_efault
|
|
__ret_efault:
|
|
ret
|
|
restore %g0, -EFAULT, %o0
|
|
|