8060ef4da9
This patch adds support to configure the AEMIF interface with supplied timing values. Since this capability is useful both from NOR and NAND flashes, it is provided as a new interface and in a file of its own. AEMIF timing configuration is required in cases: 1) Where the AEMIF clock rate can change at runtime (a side affect of cpu frequency change). 2) Where U-Boot does not support NAND/NOR but supports other media like SPI Flash or MMC/SD and thus does not care about setting up the AEMIF timing for kernel to use. 3) Where U-Boot just hasn't configured the timing values and cannot be upgraded because the box is already in the field. Since there is now a header file for AEMIF interface, the common (non-NAND specific) defines for AEMIF registers have been moved from nand.h into the newly created aemif.h Signed-off-by: Sekhar Nori <nsekhar@ti.com> Acked-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
37 lines
780 B
C
37 lines
780 B
C
/*
|
|
* TI DaVinci AEMIF support
|
|
*
|
|
* Copyright 2010 (C) Texas Instruments, Inc. http://www.ti.com/
|
|
*
|
|
* This file is licensed under the terms of the GNU General Public License
|
|
* version 2. This program is licensed "as is" without any warranty of any
|
|
* kind, whether express or implied.
|
|
*/
|
|
#ifndef _MACH_DAVINCI_AEMIF_H
|
|
#define _MACH_DAVINCI_AEMIF_H
|
|
|
|
#define NRCSR_OFFSET 0x00
|
|
#define AWCCR_OFFSET 0x04
|
|
#define A1CR_OFFSET 0x10
|
|
|
|
#define ACR_ASIZE_MASK 0x3
|
|
#define ACR_EW_MASK BIT(30)
|
|
#define ACR_SS_MASK BIT(31)
|
|
|
|
/* All timings in nanoseconds */
|
|
struct davinci_aemif_timing {
|
|
u8 wsetup;
|
|
u8 wstrobe;
|
|
u8 whold;
|
|
|
|
u8 rsetup;
|
|
u8 rstrobe;
|
|
u8 rhold;
|
|
|
|
u8 ta;
|
|
};
|
|
|
|
int davinci_aemif_setup_timing(struct davinci_aemif_timing *t,
|
|
void __iomem *base, unsigned cs);
|
|
#endif
|